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Showing 1 to 9 of 9 for “"SCMP"”.

  1. Application Benchmarks for SCMP: Single Chip Message-Passing Computer

    … multiple processors on a single chip. The SCMP system being developed at Virginia Tech includes up to 64 processors on a chip, connected in a 2-D mesh. On-chip memory is included with each processor, and the architecture includes support for communication and the execution of parallel …

    vt Repository record for Application Benchmarks for SCMP: Single Chip Message-Passing Computer (opens in a new tab)

  2. Implementation of a Hardware-Optimized MPI Library for the SCMP Multiprocessor

    … solution is the Single-Chip Message-Passing (SCMP) Parallel Computer, developed at Virginia Tech. SCMP makes use of an architecture where a number of simple processors are tiled across a single chip and connected by a fast interconnection network. The system is designed to take advantage of …

    vt Repository record for Implementation of a Hardware-Optimized MPI Library for the SCMP Multiprocessor (opens in a new tab)

  3. The Design of the Node for the Single Chip Message Passing (SCMP) Parallel Computer

    … to limit the length of the wires on a chip. The SCMP parallel computer is a new architecture that is made up of small processing elements, called nodes, which are connected in a 2-D mesh with nearest neighbor connections. Nodes communicate with one another, via message passing, through a network, …

    vt Repository record for The Design of the Node for the Single Chip Message Passing (SCMP) Parallel Computer (opens in a new tab)

  4. Support for Send-and-Receive Based Message-Passing for the Single-Chip Message-Passing Architecture

    … modifying the Single-Chip Message-Passing (SCMP) architecture to more efficiently support send-and-receive based message-passing. The proposed system is compared, for performance and programmability, to the active messaging programming model currently used by SCMP. SCMP offers a unique …

    vt Repository record for Support for Send-and-Receive Based Message-Passing for the Single-Chip Message-Passing Architecture (opens in a new tab)

  5. Designing a Compiler for a Distributed Memory Parallel Computing System

    The SCMP processor presents a unique approach to processor design: integrating multiple processors, a network, and memory onto a single chip. The benefits to this design include a reduction in overhead incurred by synchronization, communication, and memory accesses. To properly determine its …

    vt Repository record for Designing a Compiler for a Distributed Memory Parallel Computing System (opens in a new tab)

  6. High Performance Applications for the Single-Chip Message-Passing Parallel Computer

    … challenges is the Single-Chip Message-Passing (SCMP) Parallel Computer, developed at Virginia Tech. SCMP is a unique, tiled architecture aimed at thread-level parallelism (TLP). Identical cores are replicated across the chip, and global wire traces have been eliminated. The nodes are connected …

    vt Repository record for High Performance Applications for the Single-Chip Message-Passing Parallel Computer (opens in a new tab)

  7. Balancing Performance, Area, and Power in an On-Chip Network

    … applications. The Single-Chip Message Passing (SCMP) parallel computer sits at the confluence of these trends. SCMP is a tiled architecture consisting of numerous thread-parallel processor and memory nodes connected through a structured interconnection network. Using an interconnection network …

    vt Repository record for Balancing Performance, Area, and Power in an On-Chip Network (opens in a new tab)

  8. Evaluating the Design and Performance of a Single-Chip Parallel Computer Using System-Level Models and Methodology

    … level. The new Single-Chip, Message-Passing (SCMP) parallel computer is a tightly coupled mesh of processing nodes that is designed to exploit thread-level parallelism as efficiently as possible. By minimizing the latency of communication among processors, memory access time, and the time for …

    vt Repository record for Evaluating the Design and Performance of a Single-Chip Parallel Computer Using System-Level Models and Methodology (opens in a new tab)

  9. Microarchitectural Level Power Analysis And Optimization In Single Chip Parallel Computers

    … on the Single Chip Message-Passing Parallel (SCMP) Computer and can be extended to other Single Chip Parallel Computers. The thesis focuses on the development of power estimation models, construction of the power analysis tool, study of the power advantages of the architecture and …

    vt Repository record for Microarchitectural Level Power Analysis And Optimization In Single Chip Parallel Computers (opens in a new tab)