Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 34 for “"SAR ADC"”.
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Low-power SAR ADC for biomedical portable devices
… and no more. Successive-Approximation-Register (SAR) Analog to Digital Converters (ADCs) stand out as the preferred choice for such applications due to their remarkable energy efficiency and nearly digital architecture. The SAR architecture’s scalability allows for energy consumption optimisation …
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A 1.7GS/s SAR ADC in 28nm CMOS
This thesis presents a 1.7GS/s 9b single channel SAR ADC in 28nm CMOS technology. The main focus of the thesis is the leveraging of the pipelining, passive residue transfer, and partial interleaving techniques to increase sample rate of the ADC. The first chapter explains the motivation for …
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A highly digital, reconfigurable and voltage scalable SAR ADC
… reconfigurable analog-to-digital converter (ADC) is needed to digitize a wide range of signals with varying bandwidth and resolution requirements. This thesis describes the design of an ADC whose power scales exponentially with resolution and linearly with frequency to maximize the system …
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Low-power high-performance SAR ADC design with digital calibration techniques
… successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static …
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An on-chip input driver for a high-voltage SAR ADC
… the design of a novel on-chip input driver for a SAR ADC. The driver achieves performance gains relative to off-chip alternatives by being integrated into the signal path of the ADC between the sampling switches and sampling capacitor. This placement allows for auto-zeroing the offset of the …
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Low-power high-performance SAR ADC with redundancy and digital background calibration
… make the successive- approximation-register (SAR) architecture an attractive alternative for applications that require high-speed and high-accuracy analog-to-digital converters (ADCs). In SAR ADCs, the key linearity and speed limiting factors are capacitor mismatch and incomplete …
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Investigation and design of key circuit blocks in a 10 bit SAR ADC at 100 MS/s
… circuit blocks in a high speed, high resolution SAR ADC in TSMC’s 28nm technology. The research carried out analyses the circuit limitations of the switched capacitor DAC and the settling problems of the reference voltage associated with a switched capacitor scheme. The switched capacitor DAC is …
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Design of High-Resolution SAR ADC for Detection of Sub-Cortical Neuron Action Potentials for BMI Applications
… low-power successive approximation register (SAR) analog-to-digital converter (ADC) tailored for sub-cortical neural signal detection. To optimize dynamic range and reduce power consumption, a novel adaptive zoom-and-tracking architecture is introduced, enabling the ADC to dynamically adjust …
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Design port and optimization of a high-speed SAR ADC comparator from 65nm to 0.11[mu]M
… comparator circuit for use in a digital camera SAR ADC has been ported from its original 65nm process to a 0.11[mu]m process. Its design has been analyzed and performance presented here. Additionally, an alternative latch-only architecture for the comparator has been designed and analyzed. In …
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Secure analog-to-digital conversion against power side-channel attack
… analog circuits and a digital processor, an ADC can create a critical hardware security loophole. By exploiting the power side-channel leakage of the ADC, an attacker can expose the private signal chain data. Having recognized the security threat, this thesis explores both aspects of the SAR …
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Design of residue amplifiers for high-speed pipelined-SAR ADCs
… Gm-R residue amplifier used in a pipelined-SAR ADC, implemented in a 28nm CMOS process. The proposed design achieves good linearity and low gain variation due to temperature using a constant-gm biasing network. The thesis is organized as follows: Chapter 1 introduces the concepts of ADCs and …
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Successive-approximation-register based quantizer design for high-speed delta-sigma modulators
… multi-bit successive-approximation-register (SAR) quantizers. Design techniques for high-speed medium-resolution SAR analog-to-digital converters (ADCs) using synchronous SAR logic are proposed. Four-bit and 8-bit 5 GS/s SAR ADCs have been implemented in 65 nm CMOS using 8-channel and …
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Cmos Design of an 8-Bit 1MS/S Successive Approximation Register ADC
… of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance.</p> <p>This thesis presents an 8-bit successive approximation …
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Design Techniques for High-Performance SAR A/D Converters
… of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs …
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Design of a low power switched-capacitor pipeline analog-to-digital converter
<p>An Analog to Digital Converter (ADC) is a circuit which converts an analog signal into digital signal. Real world is analog, and the data processed by the computer or by other signal processing systems is digital. Therefore, the need for ADCs is obvious.</p><p>In this thesis, several novel …
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Low power data acquisition for microImplant biometric monitoring of tremors
… the demand on the energy source. A low energy SAR ADC is designed using adiabatic charging to further reduce energy usage. This application is ideal for adiabatic techniques because of the low frequency of operation and the ease with which we can reclaim energy from discharging the capacitors. …
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Energy-efficient data converter design in scaled CMOS technology
… In the first part, a power-efficient 10-bit SAR ADC featured with a gain-boosted dynamic comparator is presented. In energy-constrained applications, the converter is usually supplied with low supply voltage (e.g., 0.3 V-0.5 V), which reduces the comparator pre-amplifier (pre-amp) gain and …
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Silicon Germanium BiCMOS Comparator Designed for Use in An Extreme Environment Analog to Digital Converter
… circuit was also used as a building block in a SAR ADC that would be used for extreme environments.</p>
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Mixed-Signal Architectures for Spectrum Sensing
… reducing the analog-to-digital converter (ADC) sampling rate. The integrating mixer is a novel mixed-signal architecture for spectrum sensing that is based on the short-time Fourier transform (STFT). The architecture consists of a folded double balanced mixer with capacitive loads that …
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