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Showing 1 to 14 of 14 for “"Run-Time Reconfiguration"”.

  1. Wormhole Run-Time Reconfiguration: Conceptualization and VLSI Design of a High Performance Computing System

    … in the Colt CCM. By offering word grain reconfiguration and the ability to partially reconfigure at computational element resolution, the Colt can offer higher effective utilization over traditional FPGAs. Further, the majority of the pins of the Colt can be used for both normal I/O and …

    vt Repository record for Wormhole Run-Time Reconfiguration: Conceptualization and VLSI Design of a High Performance Computing System (opens in a new tab)

  2. Context Switching Strategies in a Run-Time Reconfigurable system

    A distinctive feature of run-time reconfigurable systems is the ability to change the configuration of programmable resources during execution. This opens a number of possibilities such as virtualisation of computational resources, simplified routing and in certain applications lower power. …

    vt Repository record for Context Switching Strategies in a Run-Time Reconfigurable system (opens in a new tab)

  3. Dynamic Module Library Generation for FPGA-based Run-Time Reconfigurable Systems

    … Gate Arrays (FPGAs) can implement entire run-time reconfigurable systems using partial reconfiguration. Module-based run-time reconfiguration permits the construction of custom applications at run-time using pre-compiled Intellectual Property (IP) from a module library. The need for both …

    vt Repository record for Dynamic Module Library Generation for FPGA-based Run-Time Reconfigurable Systems (opens in a new tab)

  4. A Multiplexed Memory Port for Run Time Reconfigurable Applications

    … inefficient. The difficulties of implementing run time reconfiguration (RTR) on CCMs are addressed in this thesis. Tools and techniques are introduced to simplify the development and synthesis of applications and partitions for RTR applications. A multiplexed memory port (MMP) is presented in …

    vt Repository record for A Multiplexed Memory Port for Run Time Reconfigurable Applications (opens in a new tab)

  5. Framework for Hardware Agility on FPGAs

    … and universities has successfully developed run-time reconfiguration tools to make FPGA designs more flexible and thus vastly reducing configuration times. Developers now have a more powerful platform with dense Digital Signal Processor resources and the flexibility of SDR. Xilinx offers …

    vt Repository record for Framework for Hardware Agility on FPGAs (opens in a new tab)

  6. A Genetic Algorithm-Based Place-and-Route Compiler For A Run-time Reconfigurable Computing System

    … experimental computing model known as wormhole run-time reconfiguration allows for partial reconfiguration and is highly scalable. In this approach, configuration information and data are grouped together in a computing unit called a stream, which can tunnel through the chip creating a series of …

    vt Repository record for A Genetic Algorithm-Based Place-and-Route Compiler For A Run-time Reconfigurable Computing System (opens in a new tab)

  7. Architecture-Independent Design for Run-Time Reconfigurable Custom Computing Machines

    … This technique is commonly referred to as run-time reconfiguration. Widespread acceptance of run-time reconfigurable custom computing depends upon the existence of high-level automated design tools. Given the wide variety of available platforms and the rate that the technology is evolving, …

    vt Repository record for Architecture-Independent Design for Run-Time Reconfigurable Custom Computing Machines (opens in a new tab)

  8. Reconfigurable hardware for control applications

    … FSMs on a reconfigurable device using run-time reconfiguration. The second area of research was the investigation of the characteristics of reconfigurable devices with a view to estimating the amount of hardware required within a device from high level parameters. The final area of …

    glasgow Repository record for Reconfigurable hardware for control applications (opens in a new tab)

  9. Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration

    The run-time reconfiguration of Field Programmable Gate Arrays (FPGAs) opens new avenues to hardware reuse. Through the use of process migration between hardware and software, an FPGA provides a parallel execution cache. Busy processes can be migrated into hardware-based, parallel processors, and …

    vt Repository record for Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration (opens in a new tab)

  10. The Effects of Caching on Reconfigurable Adaptive Computing Systems

    … are available. One solution to this problem is runtime reconfiguration (RTR). Using RTR techniques, a large algorithm is implemented as a collection of configurations for the reconfigurable hardware. These configurations are loaded onto the reconfigurable hardware as necessary to implement the …

    vt Repository record for The Effects of Caching on Reconfigurable Adaptive Computing Systems (opens in a new tab)

  11. Design and Implementation of a Soft Radio Architecture for Reconfigurable Platforms

    … with the use of stream based processing and run-time reconfigurable hardware. These choices aid in maximizing performance with minimum hardware while keeping the architecture robust, simple, and scalable. The reconfigurable platform enables {em hardware paging} through reusability hardware. …

    vt Repository record for Design and Implementation of a Soft Radio Architecture for Reconfigurable Platforms (opens in a new tab)

  12. Framework for a Context-Switching Run-Time Reconfigurable System

    … machines has led to a wealth of research in run-time reconfigurable systems and applications. A limitation often encountered in this research is the slow configuration time with respect to the system clock speed. One technique to deal with these configuration delays has been to develop …

    vt Repository record for Framework for a Context-Switching Run-Time Reconfigurable System (opens in a new tab)

  13. FPGA structures for high speed and low overhead dynamic circuit specialization

    … However, modern techniques such as Partial Reconfiguration (PR) enable us to configure a part in the configuration memory with partial bitstreams during run-time. The reconfiguration is achieved by swapping in partial bitstreams into the configuration memory via a configuration interface …

    ghent Repository record for FPGA structures for high speed and low overhead dynamic circuit specialization (opens in a new tab)