Global ETD Search
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Showing 1 to 3 of 3 for “"Risc-v Architecture"”.
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Implementation of Intermittent-robust Computing on RISC-V Architecture
… energy harvesting highlights the need for architectures capable of sustaining correct and reliable execution under frequent and unpredictable power interruptions. This thesis addresses this challenge by proposing RISE (RISC-V Intermittent System Extensions), an architectural and ISA-level …
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Efficient spatial and temporal safety for microcontrollers and application-class processors
… implementation of Capability Hardware Enhanced RISC Instructions (CHERI) secure capabilities for RISC-V microarchitectures. This includes implementations for three different scales of core, including microcontrollers and the first open application of CHERI to a superscalar processor. Tradeoffs …
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Graph-based microarchitecture exploration: Automated optimization on RISC-V hardware
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms