Global ETD Search

High-Level Resource Binding and Allocation for Power and Performance Optimization

Cromar, Scott A.University of Illinois at Urbana-Champaign2009

… of abstraction. In this thesis, we present two resource binding and allocation algorithms that take advantage of the optimization opportunities available at the higher level of abstraction. The first is a new variation-aware high-level synthesis binding and module selection algorithm, named …

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Temperature and Interconnect Aware Unified Physical and High Level Synthesis

Krishnan, VyasDigital Commons @ University of South Florida2008

… with temperature-aware task scheduling, resource binding, and floorplanning. Compared to conventional low-power synthesis methods, our approach is effective in synthesizing circuits with lower chip temperatures and more uniform thermal distributions, with temperature reductions up to 23% …

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A Methodology to Design Pipelined Simulated Annealing Kernel Accelerators on Space-Borne Field-Programmable Gate Arrays

Carver, Jeffrey Michael

utahstate Repository record for A Methodology to Design Pipelined Simulated Annealing Kernel Accelerators on Space-Borne Field-Programmable Gate Arrays (opens in a new tab)