Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 21 for “"Register file"”.
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Energy-efficient register file design
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2000.
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Energy-efficient mechanisms for managing on-chip storage in throughput processors
… efficiency. Modern GPUs contain very large register files that consume between 15%-20% of the processor's dynamic energy. Most values written into the register file are only read a single time, often within a few instructions of being produced. To optimize for these patterns, we explore …
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Power estimation and power optimization policies for processor-based systems
… that, reducing the power consumption in the register file of the processor architecture was the goal of the research. Given that the register file is one of the most power-hungry devices, firstly an efficient hardware mechanism to tum the unused registers of the register file into a low power …
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Development and evaluation of a simultaneous multithreading processor simulator
… The second part of this thesis explores the register file for SMT processors. The register file size grows with increased issue widths, instruction window sizes, and number of thread contexts; as the register file size increases, so does its access latency. Solutions to the register file …
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Early Power Estimation for VLSI Circuits
Power estimation for register files at the microarchitectural level requires predictions of activity and capacitance of power hungry nodes in the register file. Both of these predictors are developed in this research, thus making it possible to estimate power for multiported, pipelined register …
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Soft-error resilient on-chip memory structures
… such as L1 data/instruction caches and register files, have become an increasing challenge in designing new generation reliable microprocessors. Due to their transient/random nature, soft errors cannot be captured by traditional verification and testing process due to the irrelevancy to …
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Cluster assignment and instruction scheduling for partitioned register-set machines
… constraint enters the picture---the number of register-file ports needed grows directly with the number of functional units. At some point, the multiplexing logic on register ports can come to dominate the processor's cycle time. A reasonable solution is to partition the register file into …
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Design and Analysis of an Asynchronous Microcontroller
… reduce MTNCL pipeline activity and improve MTNCL register file area and power consumption are introduced. The results show the MTNCL design to have superior leakage power characteristics. The area and active energy comparisons highlight the need for better MTNCL logic synthesis techniques.</p>
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Exposing datapath elements to reduce microprocessor energy consumption
… energy consumption. We focus on eliminating register file traffic by exposing the latches in the bypass network, as our study shows that there is potential for significant benefit by doing this. We present the idea of software restart markers to handle the exception management overhead that …
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Multithreaded architectures for manycore throughput processors
… threads requires a complex scheduler and a large register file which is expensive to access in terms of energy and latency. With multi-level scheduling, we divide threads into a smaller set of active threads to hide short latencies and larger set of pending threads for hiding long latencies to …
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Flexible MIPS soft processor architecture
… in terms of operands, control signals and register file interaction; insert multiple redundant functional units for improved performance. The flexibility provided by the architecture allows the user to expand the processor functionality to implement instructions of coprocessor-level …
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Design and evaluation of an adaptable vector coprocessor for multicores
… function unit, a load/store unit, and a vector register file. The design was prototyped and benchmarked on a field programmable gate array (FPGA) for a multitude of configurations to evaluate the performance and power consumption. The configurations included one or two host processors and two, …
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Automatic translation of CUDA to OpenCL and comparison of performance optimizations on GPUS
… architectures of the basic compute unit, register file organization, on-chip memory limitations, DRAM coalescing patterns and floating point unit throughput of the two devices interact with each optimization differently.
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Digital System Synthesis with Complex Functional Units
… The metrics include communication buffer size, register file size, system delay, the number of buses, the number of links, and the number of multiplexers. These metrics are used to form a cost function, which is utilized by the Problem Space Genetic Partitioning algorithm (PSGP) to search for a …
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Efficient spatial and temporal safety for microcontrollers and application-class processors
… first CHERI implementations supporting a merged register file and capability mode bit. The area and frequency implications are evaluated on FPGA, and the performance and power overheads are investigated across a range of benchmarks. To validate correctness, the processors are integrated into a …
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Modular SMT-Based Verification of Rule-Based Hardware Designs
… and abstraction of the control and status register file (CSRF) and the memory system, and the use of uninterpreted functions.
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Vector processor virtualization: distributed memory hierarchy and simultaneous multithreading
… utilization for the individual threads. A vector register file (VRF) virtualization technique dynamically allocates physical vector registers to running threads. The technique is implemented for a multi-core processor embedded in an FPGA. Under the dynamic creation of threads, benchmarking …
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Instruction fusion and vector processor virtualization for higher throughput simultaneous multithreaded processors
… lengths on a multithreaded VP. With a vector register file (VRF) virtualization technique invented to dynamically allocate physical vector registers to threads, the virtualization approach improves programmer productivity by providing at run time a distinct physical register name space to each …
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Energy efficient computing exploiting data similarity and computation redundancy
… it can share most of its hardware resources with register value compression, of which adoption has been strongly promoted to reduce high power consumption of accessing the large register file. Compared with the baseline and previous scalar architectures, G-Scalar improves power efficiency by 24% …
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The trends and rates of gabapentin and pregabalin
… 2015 and 2016 were linked with the demographic file, SMR06 cancer register file, SMR01 hospital admission file, GRO death data, accident and emergency data and SMR00 outpatient file, using routine data obtained from HIC at the University of Dundee. The association of prescribing patterns with …
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