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Showing 1 to 16 of 16 for “"Reconfigurable architecture"”.

  1. Cryptarray A Scalable And Reconfigurable Architecture For Cryptographic Applications

    … for two major reasons: (i) The majority of these architectures sacrifice flexibility for performance in order to reach the performance level needed for cryptographic applications. This lack of flexibility can be detrimental considering that cryptographic standards and algorithms are still …

    ucf

  2. FleXilicon: a New Coarse-grained Reconfigurable Architecture for Multimedia and Wireless Communications

    … fails to provide sufficient computing power. Reconfigurable architectures, which have been introduced as a compromise between the two extreme solutions, have been applied successfully for multimedia and wireless communication applications. In this thesis, we investigated a new coarse-grained …

    vt Repository record for FleXilicon: a New Coarse-grained Reconfigurable Architecture for Multimedia and Wireless Communications (opens in a new tab)

  3. The design and implementation of a 3D graphics pipeline for the raw reconfigurable architecture

    … networks, and can be treated as a coarse-grained reconfigurable architecture. The graphics pipeline has four stages, and four-way parallelism in each stage, and is mapped on to a 16-tile Raw array. It supports basic rendering functions such as hardware transform and lighting, perspective correct …

    mit Repository record for The design and implementation of a 3D graphics pipeline for the raw reconfigurable architecture (opens in a new tab)

  4. The design and implementation of a workbench for application specific message-passing parallel reconfigurable architectures

    … design, simulation and evaluation of parallel reconfigurable architectures. A designer's workbench, OODRA (Object-Oriented Design of Reliable/Reconfigurable Architecture), has been implemented to realize the proposed message-passing model, and it provides a window-based, menu driven, graphics …

    uiuc Repository record for The design and implementation of a workbench for application specific message-passing parallel reconfigurable architectures (opens in a new tab)

  5. Uma heurística gulosa para Modulo Scheduling em arquiteturas reconfiguráveis em tempo de execução

    … grosso também chamadas de CGRA (Coarse Grained Reconfigurable Architecture), tem sido propostas para tentar tratar esse grande fluxo de dados, levando em con- sideração também a necessidade de eficiência em termos de potência, energia e desempenho. Um dos desafios é o mapeamento dos laços de …

    brazil-ufv Repository record for Uma heurística gulosa para Modulo Scheduling em arquiteturas reconfiguráveis em tempo de execução (opens in a new tab)

  6. Architecture study of a 3D CMOS-NEM FPGA

    In this paper, we introduce a reconfigurable architecture, named 3D CMOS-NEM FPGA, which utilizes nanoelectromechanical (NEM) relays and 3D integration techniques synergistically. Unique features of our architecture include: hybrid CMOS-NEM FPGA look-up tables (LUTs) and con gurable logic blocks …

    uiuc Repository record for Architecture study of a 3D CMOS-NEM FPGA (opens in a new tab)

  7. VLSI Implementation of a Wormhole Runtime Reconfigurable Processor

    … innovations. Among these, the wormhole runtime reconfigurable architecture introduces the concept of stream processing. It enables dynamic reconfiguration of hardware with little overheads and is very much suited for data-path based computations with deep computational pipelines. Stallion, …

    vt Repository record for VLSI Implementation of a Wormhole Runtime Reconfigurable Processor (opens in a new tab)

  8. Digital signal processing platform based on a novel dynamically reconfigurable array

    Dynamically reconfigurable processors are attracting significant interest in the semiconductor industry as they are promising to provide a new level of trade-off between the conflicting parameters of performance, flexibility, silicon area, power consumption and Non-Recurring Engineering (NRE) …

    glasgow

  9. FPGA Prototyping Framework on ARROW SoCKit Board with Xillybus Interface and Standard FIFO

    … designs. Furthermore, a system-on-chip (SoC) architecture that integrates traditional processors with FPGA fabrics enables a hybrid reconfigurable architecture that the FPGA may be re-purposed as needed on the fly. These advantages in FPGA applications inspire this thesis in presenting a …

    houston Repository record for FPGA Prototyping Framework on ARROW SoCKit Board with Xillybus Interface and Standard FIFO (opens in a new tab)

  10. MURAC: A unified machine model for heterogeneous computers

    … advantages of multiple distinct processing architectures to be efficiently exploited within a single machine. These systems are capable of delivering large performance increases by matching the applications to architectures that are most suited to them. The Multiple Runtime-reconfigurable

    cape-town Repository record for MURAC: A unified machine model for heterogeneous computers (opens in a new tab)

  11. Real-time control architecture for a multi UAV test bed

    … purpose of this thesis is to develop a control architecture running at real-time for a multi unmanned aerial vehicle test bed formed by three AscTec Hummingbird mini quadrotors. The reliable and reconfigurable architecture presented here has a FPGA-based embedded system as main controller. Under …

    unm Repository record for Real-time control architecture for a multi UAV test bed (opens in a new tab)

  12. Reconfigurable and heterogeneous architectures for efficient computing

    … these inefficiencies. Our solution is novel reconfigurable GPU architecture that can adapt to the needs of GPUs by dynamically allocating computational and memory resources among GPU cores (SMs). Second, we consider the limitations of dynamic partial reconfiguration (DPR) in modern FPGAs. We …

    uiuc Repository record for Reconfigurable and heterogeneous architectures for efficient computing (opens in a new tab)

  13. Design and resource management of reconfigurable multiprocessors for data-parallel applications

    FPGA (Field-Programmable Gate Array)-based custom reconfigurable computing machines have established themselves as low-cost and low-risk alternatives to ASIC (Application-Specific Integrated Circuit) implementations and general-purpose microprocessors in accelerating a wide range of …

    njit Repository record for Design and resource management of reconfigurable multiprocessors for data-parallel applications (opens in a new tab)

  14. Circuit Design Methods with Emerging Nanotechnologies

    … logic implementation. Based on the PLEs, a reconfigurable architecture is constructed to offer dynamic reconfigurability with little or no reconfiguration overhead, due to the intrinsic self-latching property of nanopipelining. Our reconfiguration data generation algorithm can further reduce …

    vt Repository record for Circuit Design Methods with Emerging Nanotechnologies (opens in a new tab)

  15. Bistable Auxetic System -- Programming synclastic curvature into 2D Patterning

    … of thinking about the ever-expanding quest in architecture to deliver free-form geometry. Rather than relying on complex formwork, the proposed reconfigurable system can translate free form synclastic surfaces to pre-programmed 2D configuration, providing an attractive potential for the …

    cornell Repository record for Bistable Auxetic System -- Programming synclastic curvature into 2D Patterning (opens in a new tab)

  16. Energy Proportional Future Chip-to-chip Computing Interconnect Designs

    … systems can be utilised to build a flexible, reconfigurable board-level computing platform with enhanced resource consumption and energy efficiency. Optical interconnects feature high IO capacity, distance-independent energy consumption, and low-delay connection. Optical linking fabric allows …

    cambridge Repository record for Energy Proportional Future Chip-to-chip Computing Interconnect Designs (opens in a new tab)