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Showing 1 to 17 of 17 for “"Reconfigurable Logic"”.

  1. Reconfigurable logic test methodologies for ISDN

    This portfolio presents three separate design and development projects. Each project addresses a different aspect of ISDN testing. Field programmable gate array (FPGA) technology was employed to facilitate the development. The design and development work produced a hardware platform that could be …

    southwales Repository record for Reconfigurable logic test methodologies for ISDN (opens in a new tab)

  2. Design synthesis for dynamically reconfigurable logic systems

    Dynamic reconfiguration of logic circuits has been a research problem for over four decades. While applications using logic reconfiguration in practical scenarios have been demonstrated, the design of these systems has proved to be a difficult process demanding the skills of an experienced …

    bournemouth Repository record for Design synthesis for dynamically reconfigurable logic systems (opens in a new tab)

  3. Enhancing nanoscale electronics: From novel channels to reconfigurable logic circuits

    Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-12-01

    uiuc Repository record for Enhancing nanoscale electronics: From novel channels to reconfigurable logic circuits (opens in a new tab)

  4. The development of a node for a hardware reconfigurable parallel processor

    … and implementation of a node for a hardware reconfigurable parallel processor. The hardware that was developed allows for the further development of a parallel processor with configurable hardware acceleration. Each node in the system has a standard microprocessor and reconfigurable logic

    cape-town Repository record for The development of a node for a hardware reconfigurable parallel processor (opens in a new tab)

  5. Obtaining performance and programmability using reconfigurable hardware for media processing

    An imperative requirement in the design of a reconfigurable computing system or in the development of a new application on such a system is performance gains. However, such developments suffer from long-and-difficult programming process, hard-to-predict performance gains, and limited scope of …

    mit Repository record for Obtaining performance and programmability using reconfigurable hardware for media processing (opens in a new tab)

  6. Adding limited reconfigurability to superscalar processors

    … to some extent to select applications, fully reconfigurable logic can greatly improve the performance of a processor, since it is shaped for the best possible execution with the available resources. However, as reconfigurable logic is far slower than custom logic, this gain is possible only …

    epfl Repository record for Adding limited reconfigurability to superscalar processors (opens in a new tab)

  7. SOFT ADAPTIVE NANOCOMPOSITES BASED ONMETALLIC CLUSTER ASSEMBLED NETWORKS FORUNCONVENTIONAL DATA PROCESSING

    … exploited to build environmentally sensitive reconfigurable logic gates, while deposition on paper substrates demonstrated the integration of sensing and bistable electrical response on a flexible and sustainable platform.

    milano Repository record for SOFT ADAPTIVE NANOCOMPOSITES BASED ONMETALLIC CLUSTER ASSEMBLED NETWORKS FORUNCONVENTIONAL DATA PROCESSING (opens in a new tab)

  8. Placement and routing for reconfigurable systems.

    Applications using reconfigurable logic have been widely demonstrated to offer better performance over software-based solutions. However, good performance rating is often destroyed by poor reconfiguration latency - time required to reconfigure hardware to perform the new task. Recent research focus …

    bournemouth Repository record for Placement and routing for reconfigurable systems. (opens in a new tab)

  9. Energy-aware architectures, circuits and CAD for field programmable gate arrays

    … Gate Arrays (FPGAs) are a class of hardware reconfigurable logic devices based on look-up tables (LUTs) and programmable interconnect that have found broad acceptance for a wide range of applications. However, power consumption is one of the leading obstacles to broader adoption of FPGAs in …

    mit Repository record for Energy-aware architectures, circuits and CAD for field programmable gate arrays (opens in a new tab)

  10. FPGA-based hardware acceleration for a key-value store database

    … a key-value database. Utilized as a platform of reconfigurable logic, the FPGA offers massively parallel usability at a much faster pace than a traditional software-enabled database system. This project implements a key-value store database hardware accelerator in order to investigate the …

    mit Repository record for FPGA-based hardware acceleration for a key-value store database (opens in a new tab)

  11. A Framework for the Design and Generation of Spatial MFSA Accelerators: The SPARX Approach

    … into a single flow, mapping merged automata onto reconfigurable logic to combine algorithmic compression with hardware-level concurrency.

    uic

  12. Redefining the hardware-software boundary in networked systems

    … the advent of high-performance programmable and reconfigurable logic. With these devices, developers now have the choice to develop custom hardware efficiently and cost-effectively. This thesis argues that developers now need to look at the boundary between hardware and software when developing …

    uiuc Repository record for Redefining the hardware-software boundary in networked systems (opens in a new tab)

  13. Design and Implementation of a Risc-V Based LoRa Module

    … (Lattice iCE40UP5k), providing access to both reconfigurable logic and a CPU for data analytics, and standard interfaces for 3rd party sensors, such UART, I2C and SPI. The whole design is integrated on a custom PCB in a USB dongle form factor. The resulting prototype can therefore be used as a …

    cape-town Repository record for Design and Implementation of a Risc-V Based LoRa Module (opens in a new tab)

  14. Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems

    … is designed using minimal resources from the reconfigurable logic of an FPGA. The secondary I/O processor is implemented on an incipient Zynq SoC based flight controller. The soft-core microprocessor running on the configurable logic of the FPGA serves as a first level check on the sensor data …

    vt Repository record for Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems (opens in a new tab)

  15. A Dynamically Reconfigurable Parallel Processing Framework with Application to High-Performance Video Processing

    … leads to the consideration of dynamically reconfigurable systems. The goal of this dissertation research was to develop and demonstrate the viability of integrated parallel processing system that effectively and efficiently apply pre-optimized hardware cores for processing video streamed …

    unm Repository record for A Dynamically Reconfigurable Parallel Processing Framework with Application to High-Performance Video Processing (opens in a new tab)

  16. Design and resource management of reconfigurable multiprocessors for data-parallel applications

    FPGA (Field-Programmable Gate Array)-based custom reconfigurable computing machines have established themselves as low-cost and low-risk alternatives to ASIC (Application-Specific Integrated Circuit) implementations and general-purpose microprocessors in accelerating a wide range of …

    njit Repository record for Design and resource management of reconfigurable multiprocessors for data-parallel applications (opens in a new tab)

  17. Twill: A Hybrid Microcontroller-FPGA Framework for Parallelizing Single- Threaded C Programs

    … both micropro- cessors and re-programmable logic are being utilized across several fields ranging from the automotive industry to network infrastructure. Unfortunately, the de- velopment tools accompanying these products leave much to be desired, requiring knowledge of both traditional …

    calpoly Repository record for Twill: A Hybrid Microcontroller-FPGA Framework for Parallelizing Single- Threaded C Programs (opens in a new tab)