Global ETD Search
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Showing 1 to 5 of 5 for “"Random jitter"”.
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Techniques for low jitter clock multiplication
… Loops (MDLL), offer significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is achieved by introducing the reference signal directly into their voltage controlled oscillators (VCO) to realign the phase to the clean reference. However, the typical cost of this …
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Models predicting the performance of IC component or PCB channel during electromagnetic interference
… cover the prediction of the characteristics of jitter due to crosstalk and due to simultaneous switching noise, and covers susceptibility of delay locked loop (DLL) to electromagnetic interference.</p> <p>In the first paper, an improved tail-fit de-convolution method is proposed for …
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Clock multiplication techniques for high-speed I/Os
Generation of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by …
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Stochastic modeling in computational electromagnetics
… problems, defined in terms of correlated random variables, is alleviated with a random-space dimensionality reduction technique that, in combination with an a-priori sensitivity assessment, results in an accurate technique for the statistical characterization and yield estimation of …
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Systems and circuits for broadband contactless and wireline transceivers
… is introduced to fully detect the deterministic jitter (DJ) in the output clock at much lower speeds with minimal power overhead. An orthogonal 3-path LMS-based adaptation algorithm is implemented to suppress the DJ using 5 fs-resolution digital to time converters (DTCs) at the quadrupler input. …