Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 8 of 8 for “"RTL design"”.
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Goldmine: An integration of data mining and static analysis for automatic generation of hardware assertions
… static analysis of the Register Transfer Level (RTL) design. The RTL design is first simulated to generate data about the design’s dynamic behavior. The generated data is then mined for ""candidate assertions"" that are likely to be invariants. We present both a decision tree supervised learning …
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Optimizing Verification of RTL Designs Using Reinforcement Learning Methods
… in the last sixty years has today enabled the design of highly complex digital systems on a single semiconductor chip. Due to the great cost of semiconductor chip projects, ensuring these digital systems work first-time is paramount. Digital verification paradigms and techniques have therefore …
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Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution
Over the last two decades, chip design has been conducted at the register transfer (RT) Level using Hardware Descriptive Languages (HDL), such as VHDL and Verilog. The modeling at the behavioral level not only allows for better representation and understanding of the design, but also allows for …
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Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications
<p>This thesis presents a design flow from specifications and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1 kilobyte that are suitable for lunar environments. The design uses the IBM SiGe 5AM BiCMOS 0.5 micron process for a synchronous memory system capable of …
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Energy-efficient speaker identification with low-precision networks
… identification models. Second, I build an RTL design for efficient evaluation of a subset of our speaker ID models. In particular, I design, implement, and benchmark architectures for low-precision fixed point neural network evaluation and ternary network evaluation. Compared to a baseline …
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Harmonizing data mining and static analysis to tackle hardware and system level verification
… one of the greatest challenges for today's chip design. Formal verification and simulation-based verification have been widely adopted. Both of them always rely on assertions (a.k.a. properties) to express a design's intended behaviors. State-of-the-art formal verification suffers from the …
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Statistical guarantees of performance for RTL designs
… process that verifies the adherence of a design to a non-probabilistic performance specification. However, adaptive techniques like voltage and frequency scaling, process variations due to shrinking chip geometries and input variations for accommodating ""better-than-worst-case"" design …
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Cache design exploration in a general purpose massively parallel architecture
Memory model design is a major part of any modern processor architecture. There are many design choices and tradeoffs to be considered, and these often need to be tightly coupled to the processing unit's arcitecure. The increased popularity of massively parallel architectures has motivated …