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Showing 1 to 4 of 4 for “"RTL Simulation"”.
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Task Scheduling Techniques to Accelerate RTL Simulation
Fast simulation of digital circuits is crucial to build modern chips. Slow simulation lengthens chip design time and makes bugs more frequent. While simulation can happen at different levels of abstraction, Register-Transfer-Level (RTL) simulation is the usual bottleneck in chip design, as it is …
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Accelerating RTL Simulation Through Fine-grained Task Dataflow and Selective Execution
Fast simulation of digital circuits is crucial to build modern chips. Current processors and SoCs integrate hundreds of complex components, including cores, accelerators, and memory hierarchies. Simulating these systems is necessary to verify correctness and explore the design space. Simulation can …
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Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration
… to the acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed. RTL code can exhibit a form of locality of reference such that executing processes tend to be executed again. This property is termed executive temporal locality, and it can be exploited by …
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Directoryless shared memory architecture using thread migration and remote access
… the ASIC implementation details as well as RTL simulation results of the Execution Migration Machine (EM² ), a 110-core directoryless shared-memory processor.