Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 81 for “"RTL"”.
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Static Analysis to improve RTL Verification
Integrated circuits have traveled a long way from being a general purpose microprocessor to an application specific circuit. It has become an integral part of the modern era of technology that we live in. As the applications and their complexities are increasing rapidly every day, so are the sizes …
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Statistical guarantees of performance for RTL designs
… can be applied at the register transfer level (RTL), it would facilitate better choices early in the hardware design cycle. In this thesis, we introduce the SHARPE (Statistical High-level Analysis and Rigorous Performance Estimation) methodology. Our SHARPE methodology is a rigorous, systematic …
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Task Scheduling Techniques to Accelerate RTL Simulation
… levels of abstraction, Register-Transfer-Level (RTL) simulation is the usual bottleneck in chip design, as it is needed for ongoing debugging and evaluation. Current simulators scale poorly across CPU cores, because they are unable to exploit the fine-grained parallelism inherent in simulation …
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Guiding RTL Test Generation Using Relevant Potential Invariants
… validation at the Register Transfer Level (RTL). Providing useful guidance to the test generator for such techniques is critical. In our approach, we provide guidance by exploiting potential invariants in the design. These potential invariants are obtained using random stimuli such that they …
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RTL Functional Test Generation Using Factored Concolic Execution
… by transforming the Register Transfer Level (RTL) source for the design into a high-performance C++ compiled functional simulator which is instrumented for branch coverage. An exploration begins by simulating the design with concrete stimuli. Then, we perform an interleaved cycle-by-cycle …
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Optimizing Verification of RTL Designs Using Reinforcement Learning Methods
… designs modelled at the Register Transfer Logic (RTL) level is the ‘simulation based constrained random coverage driven functional verification’. This paradigm is abbreviated as CFV in this research. While greatly enhancing the verification process for the bulk of the RTL design, reaching full …
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Increasing Branch Coverage with Dual Metric RTL Test Generation
… we present a new register-transfer level (RTL) test generation method that makes use of two coverage metrics, Branch Coverage, and Mutation Coverage across two stages, to cover hard-to-reach points previously unreached. We start with a preprocessing stage by converting the RTL source to a …
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Microarchitecture Categorization and Pre-RTL Analytical Modeling for Sparse Tensor Accelerators
… Sparseloop succeeds at analytical pre-RTL modeling of architecture-level metrics for sparse tensor accelerators, accurately capturing the beneficial impact of SAFs on overall design cost. However, Sparseloop lacks cost models for microarchitectural primitives and design topologies …
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Accelerating RTL Simulation Through Fine-grained Task Dataflow and Selective Execution
… this work we focus on Register-Transfer-Level (RTL) simulation. While RTL simulators are frequently used in development due to their quick compilation times, their runtime performance is slow. This is because as the designs are scaled up, multicore communication and scheduling overheads limit …
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Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution
… Despite these benefits, validating a RTL design is not necessarily easier. Today, design validation is considered one of the most time and resource consuming aspects of hardware design. The high costs associated with late detection of bugs can be enormous. Together with stringent time …
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Improving Branch Coverage in RTL Circuits with Signal Domain Analysis and Restrictive Symbolic Execution
… stimuli generation for Register Transfer Level (RTL) circuits. However, stimuli generation frameworks are still not capable of generating effective stimuli for all circuits. Some of the limiting factors are 1) It is hard to ascertain if a branch in the RTL code is reachable, and 2) Some …
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Reachability Analysis of RTL Circuits Using k-Induction Bounded Model Checking and Test Vector Compaction
… proving unreachability of branches in Verilog RTL code is presented. To do this, it approach uses program slicing with respect to the variables of the property under test to generate small-sized SMT formulas that describe the change of variable values between consecutive cycles. Variable …
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Methodology for the formal specification of RTL RISC processor designs (with particular reference to the ARM6)
Due to the need to meet increasingly challenging objectives of increasing performance, reducing power consumption and reducing size, synchronous processor core designs have been increasing significantly in complexity for some time now. This applies to even those designs originally based on the RISC …
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Telomere Dynamics of Grey Seals (Halichoerus grypus) on Sable Island, Nova Scotia: a Long-Lived Marine Mammal Population Island
… qPCR assay to measure relative telomere length (rTL) in the grey seals (Halichoerus grypus) of Sable Island, Nova Scotia, a population of long-lived marine mammals approaching carrying capacity. Grey seals exhibited a slow decline in rTL with age, similar to other large and long-lived animals. …
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Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration
… to the acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed. RTL code can exhibit a form of locality of reference such that executing processes tend to be executed again. This property is termed executive temporal locality, and it can be exploited by …
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Branch Guided Metrics for Functional and Gate-level Testing
… has moved to the register transfer level (RTL), test methodologies at the RTL have been gaining momentum. We present a novel functional test generation framework for functional test generation at RTL. A popular software-based metric for measuring the effectiveness of an RTL test suite is …
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Goldmine: An integration of data mining and static analysis for automatic generation of hardware assertions
… static analysis of the Register Transfer Level (RTL) design. The RTL design is first simulated to generate data about the design’s dynamic behavior. The generated data is then mined for ""candidate assertions"" that are likely to be invariants. We present both a decision tree supervised learning …
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Spatial Accelerator Generation and Optimization for Tensor Applications
… between design flexibility and productivity of RTL generation: either limited to very few hand-written templates or cannot automatically generate the RTL. To address this challenge, we propose the LEGO framework, which automatically generates and optimizes spatial architecture design in the …
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Timing verification and synthesis of circuits for delay fault testability
… algorithm uses Register Transfer Level (RTL) descriptions to eliminate false paths (non-sensitizable) due to redundancy, reconvergent fanout, and control signal constraints. The RTL descriptions help to prune the search space because only valid paths are considered.
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Specification and analysis of timing properties in real-time systems
… The approach is based on Real Time Logic (RTL), a logic invented primarily for the specification of both relative and absolute timing of events. The notion of an event occurrence is central to RTL; an event occurrence marks a point in time which is of significance to the behavior of a …
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