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Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.

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Showing 1 to 20 of 41 for “"RISC-V"”.

  1. Accelerating Graphics Rendering on RISC-V GPUs

    Simpson, Joshua2023

    … a general purpose GPU (GPGPU) in the open source RISC-V ISA. The implementation features many programmable cores and texture sampling support. However, creating a truly modern GPU based on the RISC-V ISA requires the addition of fixed function hardware units for rasterization and render output …

    calpoly Repository record

  2. VLSI ARCHITECTURES FOR VIDEO PROCESSING AND RISC-V

    WALID, WALIDPolitecnico di Torino2023

    L'abstract è presente nell'allegato / the abstract is in the attachment

    poli-torino Repository record

  3. Implementation of Intermittent-robust Computing on RISC-V Architecture

    Samuele Pasquale (23291545)2025

    … addresses this challenge by proposing RISE (RISC-V Intermittent System Extensions), an architectural and ISA-level framework that enables intermittent computing on a pipelined RISC-V processor. The proposed approach introduces four lightweight hardware modules: the Intermittent Computing …

    uic

  4. The Semantics of Multicopy Atomic ARMv8 and RISC-V

    Pulte, ChristopherUniversity of Cambridge2019

    … concurrency models of the architectures ARMv8, RISC-V, and (to a lesser degree) Power. Power and early versions of ARMv8 have non-multicopy-atomic (non-MCA) concurrency models. This thesis provides abstraction results for these, including a more abstract non-MCA ARMv8 storage subsystem model, …

    cambridge Repository record

  5. Side-Channel Attacks in RISC-V BOOM Front-end

    Chavda, Rutvik JayantbhaiVirginia Tech2023

    … threat to the security of modern processors. The RISC-V BOOM core is an open-source modern processor design widely utilized in research and industry. It enables experimentation with microarchitec- tures and memory hierarchies for optimized performance in various workloads. The RISC-V BOOM core …

    vt Repository record

  6. Graph-based microarchitecture exploration: Automated optimization on RISC-V hardware

    Yuan, ChentaiUniversity of Illinois Urbana-Champaign2025

    Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms

    uiuc Repository record

  7. Design and Implementation of a Risc-V Based LoRa Module

    Njoroge, MarkDepartment of Electrical Engineering2023

    … presents the design of a prototype softcore RISC-V based LoRa end node Printed Circuit Board (PCB) design. By combining the reconfigurability and optimisation potential of a FPGA and RISC-V based architecture with a LoRa interface, the design contributes a novel option for use in solutions to …

    cape-town Repository record

  8. Brute-force resistant Pointer-Authentication using RISC-V co-processor

    Peri, Lalit PrasadVirginia Tech2025

    … (RoCC) interface [4], supporting custom RISC-V instructions PTR_SEAL and PTR_UNSEAL for sealing and authenticating pointers at runtime. Benchmark evaluation is performed using SPEC CPU2017 and SPLASH-2, with binaries instrumented through a custom LLVM pass. Experiments are conducted on …

    vt Repository record

  9. A Post-Quantum Secure RISC-V application core for IoT: from hardware design to applications

    DOLMETA, ALESSANDRAPolitecnico di Torino2025

    L'abstract è presente nell'allegato / the abstract is in the attachment

    poli-torino Repository record

  10. Accelerating Quantized DNNs with Dedicated Hardware Accelerators and RISC-V Processors Using Precision-Scalable Multipliers

    URBINATI, LUCAPolitecnico di Torino2024

    L'abstract è presente nell'allegato / the abstract is in the attachment

    poli-torino Repository record

  11. Instruction-level power consumption simulator for modeling simple timing and power side channels in a 32-bit RISC-V micro-processor

    Fang, Gloria(Gloria Yu Liang)Massachusetts Institute of Technology2021

    We create a Python based RISC-V simulator that is capable of simulating any assembly code written in RISC-V, and even perform simple power analysis of RISC-V designs. The power consumption of non-privileged RISC-V RV32IM instructions are measured experimentally, forming the basis for our simulator. …

    mit Repository record

  12. Implementace jednoduchého operačního systému

    Bucek, MatějVysoké učení technické v Brně. Fakulta informačních technologií

    … jednoduchého operačního systému pro architekturu RISC-V v jazyce C++. Systém využívá OpenSBI (SEE) a U-Boot pro zavedení a poskytuje základní funkcionalitu, včetně správy a ochrany paměti, plánování procesů, ovladačů zařízení a částečné podpory souborového systému FAT32. Výsledkem práce je funkční …

    brno-tech Repository record

  13. Design and implementation of a secure energy-efficient hardware platform for wireless sensor networks

    Waller, Madeleine(Madeleine G.)Massachusetts Institute of Technology2018

    … accelerator is used in conjunction with a RISC-V processor to provide the flexibility to implement a wide range of security protocols. This work identifies common security threats in wireless sensor networks, and presents a hardware platform used to demonstrate the energy-efficient, …

    mit Repository record

  14. A Manufacturing Methodology for Carbon Nanotube-based Digital Systems: from Devices, to Doping, to System Demonstrations

    Lau, Christian LeeMassachusetts Institute of Technology2022

    … on the open-source and commercially available RISC-V instruction set processor, running standard RISC-V 32-bit instructions on 16-bit data and addresses. It integrates >14,000 CMOS CNFETs, and operates as modern microprocessors do today (for example, it can run compiled programs; in addition, …

    mit Repository record

  15. Feasibility of Vector Instruction-Set Semantics Using Abstract Monads

    De Belen, Arthur ReinerMassachusetts Institute of Technology2024

    … formalizes a specification of a subset of the RISC-V instruction-set architecture using a general-purpose language, Haskell, using its monad and typeclass support to abstract over effects. Another member of the same family is the RISC-V V extension, which specifies instructions for operating on …

    mit Repository record

  16. Mechanized proofs that hardware is safe from timing attacks

    Duxovni, Faye(Faye Samara)Massachusetts Institute of Technology2018

    … that a given piece of code running on a given RISC-V CPU design will not leak secret inputs through timing behavior. Our system allows software and hardware to be analyzed and verified independently, and we prove that any combination of software and hardware that meet our validation criteria …

    mit Repository record

  17. Implementation of a Neural Network-Based ASIC Chip for Mobile DNA Devices

    Wu, Zhongpan2025

    … SoC architecture, based on an open-source RISC-V core, features hardware accelerators tailored for the computational demands of nanopore DNA sequencing. Performance evaluation was conducted in two stages: first through FPGA prototyping, followed by integration into a fabricated SoC. The …

    york Repository record

  18. Efficient spatial and temporal safety for microcontrollers and application-class processors

    Rugg, PeterUniversity of Cambridge2022

    … implementation of Capability Hardware Enhanced RISC Instructions (CHERI) secure capabilities for RISC-V microarchitectures. This includes implementations for three different scales of core, including microcontrollers and the first open application of CHERI to a superscalar processor. Tradeoffs …

    cambridge Repository record

  19. Defeating code reuse attacks with minimal tagged architecture

    Fingeret, Samuel (Samuel P.)Massachusetts Institute of Technology2015

    … tag memory usage. Our Taxi prototype, a modified RISC-V ISA simulator, demonstrates that we can defeat code reuse attacks with high compatibility and low memory overhead.

    mit Repository record

  20. Hardware implementation and evaluation of the Spandex cache coherence protocol

    Zhu, ZeranUniversity of Illinois at Urbana-Champaign2021

    … count respectively. We also propose the Spandex RISC-V instruction set extension, as a new interface for Spandex-aware and FCS-aware applications to convey flexible coherence performance information down to the hardware. We also provide a configuration register based interface for easily managing …

    uiuc Repository record

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