Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 139 for “"RISC"”.
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Accelerating Graphics Rendering on RISC-V GPUs
… a general purpose GPU (GPGPU) in the open source RISC-V ISA. The implementation features many programmable cores and texture sampling support. However, creating a truly modern GPU based on the RISC-V ISA requires the addition of fixed function hardware units for rasterization and render output …
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VLSI ARCHITECTURES FOR VIDEO PROCESSING AND RISC-V
L'abstract è presente nell'allegato / the abstract is in the attachment
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Quarterware: A Middleware Toolkit of Software RISC Components
The thesis also proposes Software RISC, a technique for organizing and optimizing component-based systems. The advantages of Software RISC are demonstrated using the flexibility and performance of Quarterware .
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A translator from RISC code into MC68020 code
Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1989.
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Implementation of Intermittent-robust Computing on RISC-V Architecture
… addresses this challenge by proposing RISE (RISC-V Intermittent System Extensions), an architectural and ISA-level framework that enables intermittent computing on a pipelined RISC-V processor. The proposed approach introduces four lightweight hardware modules: the Intermittent Computing …
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The Semantics of Multicopy Atomic ARMv8 and RISC-V
… concurrency models of the architectures ARMv8, RISC-V, and (to a lesser degree) Power. Power and early versions of ARMv8 have non-multicopy-atomic (non-MCA) concurrency models. This thesis provides abstraction results for these, including a more abstract non-MCA ARMv8 storage subsystem model, …
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Side-Channel Attacks in RISC-V BOOM Front-end
… threat to the security of modern processors. The RISC-V BOOM core is an open-source modern processor design widely utilized in research and industry. It enables experimentation with microarchitec- tures and memory hierarchies for optimized performance in various workloads. The RISC-V BOOM core …
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Microprocesador RISC basado en MIPS32 con conectividad AMBA AHBE-Lite
… que emplean procesadores como Cortex-M0, OpenRISC1200, ZPU y LEON3, contrastando los requisitos que cada uno insume en sus implementaciones en FPGA y el desempe~no alcanzado por cada uno.
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Graph-based microarchitecture exploration: Automated optimization on RISC-V hardware
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms
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Design and Implementation of a Risc-V Based LoRa Module
… presents the design of a prototype softcore RISC-V based LoRa end node Printed Circuit Board (PCB) design. By combining the reconfigurability and optimisation potential of a FPGA and RISC-V based architecture with a LoRa interface, the design contributes a novel option for use in solutions to …
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Brute-force resistant Pointer-Authentication using RISC-V co-processor
… (RoCC) interface [4], supporting custom RISC-V instructions PTR_SEAL and PTR_UNSEAL for sealing and authenticating pointers at runtime. Benchmark evaluation is performed using SPEC CPU2017 and SPLASH-2, with binaries instrumented through a custom LLVM pass. Experiments are conducted on …
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Accelerating the parsing process with an Application Specific VLSI RISC processor
… of designing a specialised instruction set for a RISC like processor able to accelerate the parsing and lexical analysis process, and the physical implementation of a RISC processor in CMOS VLSI technology able to execute the designed instruction set. The feasibility of mapping the process of …
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A Comparative study of RISC vs. CISC philosophies of implementing mathematical functions
A comparative study of the RISC philosophy of implementing mathematical functions vs the CISC. philosophy implementing the same functions is undertaken. This study tries to verify whether, the RISC philosophy is suited for the computers designed to run specific applications like the realtime …
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Strategic adoption of innovation--the case of reduced instruction set computer (RISC) technology
Thesis (Ph. D.)--Massachusetts Institute of Technology, Sloan School of Management, 1994.
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A Post-Quantum Secure RISC-V application core for IoT: from hardware design to applications
L'abstract è presente nell'allegato / the abstract is in the attachment
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Accelerating Quantized DNNs with Dedicated Hardware Accelerators and RISC-V Processors Using Precision-Scalable Multipliers
L'abstract è presente nell'allegato / the abstract is in the attachment
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Methodology for the formal specification of RTL RISC processor designs (with particular reference to the ARM6)
… to even those designs originally based on the RISC principle of reducing complexity in order to improve instruction throughput and the performance of the design. As designs increase in complexity, the difficulty of describing what the design does and demonstrating that the design does indeed do …
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Regulatory Mechanism of the RNAi Pathway
… to the effector RNA-induced silencing complex (RISC), wherein single-stranded siRNA guides the endoribonuclease Argonaute (Ago) to catalyze sequence-specific cleavage of complementary mRNA. It remains unclear as to what constitutes holo-RISC, how is RISC assembled and how is RISC regulated. Here …
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Instruction-level power consumption simulator for modeling simple timing and power side channels in a 32-bit RISC-V micro-processor
We create a Python based RISC-V simulator that is capable of simulating any assembly code written in RISC-V, and even perform simple power analysis of RISC-V designs. The power consumption of non-privileged RISC-V RV32IM instructions are measured experimentally, forming the basis for our simulator. …
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