Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 6 of 6 for “"RIE lag"”.
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Characterization and modeling of plasma etch pattern dependencies in integrated circuits
… arise in plasma etching due to microloading and RIE lag. This thesis contributes a semi-empirical methodology for capturing and modeling microloading, RIE lag, and related pattern dependent effects. We apply this methodology to the study of interconnect trench etching, and show that an integrated …
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Optimization of Reactive Ion Etching to Fabricate Silicon Nitride Stencil Masks in SF6 Plasma
… of the membrane using a reactive ion etch (RIE) process that determine the printed pattern. This project deals with the optimization of a sulfur hexafluoride and oxygen RIE. In this process, 0.5µm thick silicon nitride membranes are coated with 20nm of copper (hard mask) and 200nm of poly …
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Surface kinetics modeling of silicon oxide etching in fluorocarbon plasmas
… condition, many difficulties arise such as RIE lag, etch stop, and low selectivity to photoresist. For a better understanding of the process it is necessary to have an appropriate physical model to describe the surface kinetics including simultaneous etching and deposition. A novel surface …
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Fabrication of Three-Dimensionally Independent Microchannels Using a Single Mask Aimed at On-Chip Microprocessor Cooling
… using SF6 gas in a deep reactive ion etcher (DRIE) after a single etch step. The mechanism allowing for different feature depths and widths to be produced over a wafer is reactive ion etch lag, where etch rate scales with the exposed feature size in the mask. A modified Langmuir model has been …
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On-Chip Isotropic Microchannels for Cooling Three Dimensional Microprocessors
… single mask deep reactive ion etching (DRIE) process for cooling 3D ICs. Three dimensionally independent microchannels are fabricated by utilizing the RIE lag effect. This allows complex microchannel configurations to be fabricated using a single mask and single silicon etch step. …
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Three-Dimensional Passivated-Electrode Insulator-Based Dielectrophoresis (3D-PiDEP)
… utilizing an effect known as reactive ion etch lag (RIE lag). Using this unique process, 3D devices are fabricated in both silicon and the polymer polydimenthylsiloxane (PDMS). Using both numerical modeling and experimental results, we show how these 3D structures enhance the performance of the …