Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 6 of 6 for “"Power-delay Product"”.
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Predictive comparators with adaptive control
… a conventional comparator to greatly reduce the delay. A linear predictor feeds an estimated future signal to the comparator to compensate for the comparator's internal delay. On a cycle-by-cycle basis, an adaptive controller adjusts the comparator's bias current to null the error. Emphasis is …
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An ultra low power ADC for wireless micro-sensor applications
Autonomous micro-sensor nodes rely on low-power circuits to enable energy harvesting as a means of sustaining long-term, maintenance free operation. This work pursues the design of an ultra low-power analog-to-digital converter (ADC) whose sampling rate and resolution can be scaled to dynamically …
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Multiple-valued logic: technology and circuit implementation
… are also given in all the cases in terms of delay, total power, and power-delay-product (PDP). The simulation and analysis are performed using the H-SPICE tool with a GNRFET model available on the Nanohub website and CNTFET model available from Standford University website.
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Physical Modeling of Graphene Nanoribbon Field Effect Transistor Using Non-Equilibrium Green Function Approach for Integrated Circuit Design
… CMOS electronics, e.g. extremely high power density. The forward-looking solutions are the utilization of emerging materials and devices for integrated circuits. The Ph.D. dissertation focuses on graphene, one atomic layer of carbon sheet, experimentally discovered in 2004. Since …
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Efficient VLSI Implementation of Arithmetic Units and Logic Circuits
… processing units, high-speed adders with low power consumption is a requirement. Carry Select Adder (CSA) is known to be one of the fastest adders used in many data processing applications. This first contribution of the dissertation is the design of a new CSA architecture using Manchester …
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Performance variations due to layout-dependent stress in VLSI circuits
… the ensuing circuit-level variations in path delays and leakage power. Based on this analysis, layout optimization strategies are derived. In 3D-ICs, through silicon vias (TSVs) introduce unintentional thermally-induced stress in the layout, which results in placement dependent circuit …