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Showing 1 to 9 of 9 for “"Power supply noise"”.

  1. Switching mode power supply noise source impedance measurement and EMI filter characterization

    … is closely related to the impedance of the noise source. Due to the time-varying nature of the noise source impedance of an offline power supply, the measurement of it cannot be done using conventional impedance measuring methods. Two new methods, the insertion loss method and the signal …

    vt Repository record for Switching mode power supply noise source impedance measurement and EMI filter characterization (opens in a new tab)

  2. Analysis and Design of Low-Jitter Oscillators

    … oscillator types in the presence of flicker noise, white noise and power supply noise. Key results are achieved using time domain simulations to determine cycle jitter of several different oscillator architectures, semiconductor processes and component features. In the end, a design procedure …

    byu Repository record for Analysis and Design of Low-Jitter Oscillators (opens in a new tab)

  3. Models predicting the performance of IC component or PCB channel during electromagnetic interference

    … to crosstalk and due to simultaneous switching noise, and covers susceptibility of delay locked loop (DLL) to electromagnetic interference.</p> <p>In the first paper, an improved tail-fit de-convolution method is proposed for characterizing the impact of deterministic jitter in the presence of …

    must-thes Repository record for Models predicting the performance of IC component or PCB channel during electromagnetic interference (opens in a new tab)

  4. Design of power delivery networks for noise suppression and isolation using power transmission lines

    In conventional design of power delivery networks (PDNs), the PDN impedance is required to be less than the target impedance over the frequency range of interest to minimize the IR drop and to suppress the inductive noise during data transitions. As a result, most PDNs in high-speed systems consist …

    gatech Repository record for Design of power delivery networks for noise suppression and isolation using power transmission lines (opens in a new tab)

  5. Analysis of variation in on-chip waveguide distribution schemes and optical receiver circuits

    … scales because of its potential to overcome power, delay, and bandwidth limitations of traditional electrical interconnect. This thesis examines the issues of variation involved in the implementation of a robust on-chip optical signal distribution network. First, the variation within the …

    mit Repository record for Analysis of variation in on-chip waveguide distribution schemes and optical receiver circuits (opens in a new tab)

  6. Input-Pattern-Independent Estimation of Peak Current, Peak Power Dissipation, and Maximum Voltage Variation in the Power Distribution Network of VLSI Circuits

    … and the maximum voltage variation in the power distribution network. Comparisons with the results obtained by exhaustive simulation or simulation with a large number of random input vectors are also presented. In addition, design techniques for power-supply noise minimization, enhancing …

    uiuc Repository record for Input-Pattern-Independent Estimation of Peak Current, Peak Power Dissipation, and Maximum Voltage Variation in the Power Distribution Network of VLSI Circuits (opens in a new tab)

  7. Power distribution network modeling and microfluidic cooling for high-performance computing systems

    … on the silicon interposer. A numerical power distribution network (PDN) simulator is developed based on distributed circuit models for on-die power/ground grids, package- and board- level power/ground planes, and the finite difference method. The simulator enables power supply noise

    gatech Repository record for Power distribution network modeling and microfluidic cooling for high-performance computing systems (opens in a new tab)

  8. Delay Testing in Nanoscale Technology under Process Variations

    … timing-aware simulator, incorporating effects of power-supply noise and combining an event-driven logic simulation engine with interfaces to provided electrical models. MIRID aims at evaluating delay tests in presence of process variations efficiently yet accurately, by performing logic simulation …

    passau-thes Repository record for Delay Testing in Nanoscale Technology under Process Variations (opens in a new tab)

  9. Interconnect design techniques for multicore and 3D Integrated circuits.

    … computation while remaining with a stringent power envelope. Over the last decade, multicore processors have emerged as a potential solution to address some of these problems by integrating multiple smaller and more energy efficient cores in order to replace a single, larger core. These cores …

    umn Repository record for Interconnect design techniques for multicore and 3D Integrated circuits. (opens in a new tab)