Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 75 for “"Power Reduction"”.
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Peak power reduction algorithms in ADSL modems
… thesis investigates peak-to-average ratio (PAR) reduction techniques for multicarrier modulation systems, such as discrete multitone (DMT) modems and orthogonal frequency-division multiplexed (OFDM) terrestrial broadcast transmitters. Through simulation and test implementation on a …
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Shape Up: Peak -Power Reduction via Constellation Shaping
… hyperdiamond shaping reduce the unclipped peak power by 5 to 7 dB with no loss of data rate and with a symbol error rate that is virtually identical to that of conventional systems. With a clipping rate of 10-8, they still provide up to 2.8 dB of peak-power reduction. Algebraic shaping reduces …
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Peak power reduction in orthogonal frequency division multiplexing transmitters
… describes the issue of the Peak to Average Power Ratio (PAPR) in OFDM which is a major drawback, and presents new and variations to existing algorithms to reduce it.
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System specific power reduction techniques for wearable navigation technology
… to usability of the device is its excessive power consumption. As such, the goal of this work is, broadly, to- (1) Understand the largest sources of power consumption in the initial navigation proto- type system, and expose relevant features for control; (2) Develop a set of algorithms that …
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Fast peak-power reduction for MIMO-OFDM systems with diversity
A robust peak-power reduction technique called active constellation extension (ACE) reduces the peak-to-average power ratio (PAPR) of single-input single-output (SISO) orthogonal frequency-division modulated (OFDM) signals by extending the outer constellation points in a way that minimizes the PAPR …
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Power Reduction of Digital Signal Processing Systems using Subthreshold Operation
… past couple decades, the capabilities of battery-powered electronics has expanded dramatically. What started out as large bulky 2-way radios, wristwatches, and simple pacemakers, has evolved into pocket sized smart-phones, digital cameras, person digital assistants, and implantable biomedical …
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Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits
<p>In nanometer-scale CMOS technology, leakage power has become a major component of the total power dissipation due to the downscaling of threshold voltage and gate oxide thickness. The leakage power consumption has received even more attention by increasing demand for mobile devices. Since mobile …
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A power reduction algorithm for combinatorial CMOS circuits using input disabling
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
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Coordinated active power reduction strategy for voltage rise mitigation in LV distribution network
… customers, and the third party into the electric power system, most especially in the MV and LV distribution networks grew over the last decade due to the liberalization of the electricity market, rising energy demand, and increasing environmental concern. The distributed rooftop PV system …
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Implementation of delay and power reduction in deep sub-micron buses using coding
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
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Null Depth Trade Off for Output Power Reduction in a Downlink Adaptive Antenna Array
… However, downlink adaptive arrays use additional power when they are required to include null steering in their beam patterns. This excessive transmitted power reduces the effective antenna gain, increases interference in other directions and has implications on the dimensioning of the power …
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Power and performance optimization of negative capacitance transistor circuits
… technology solution for achieving extremely low power and high performance. The negative capacitance exhibited by the ferroelectric layer of the transistor results in very high effective gate capacitance leading to electrostatic voltage amplification. In other words, the internal gate voltage is …
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Estimation-theoretic framework for robust and energy-efficient system design
… of embedded computing is lack of adequate power supply. Unlike the exponential growth in computing capability, the improvements in power sources have been lackluster. Technology scaling, driven by Moore's law, has produced smaller devices that can operate on lower supply voltages; but as a …
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Matching on -Chip Data Storage to Telecommunication and Media Application Properties
… data storage savings in the range of 29% static power and 6% dynamic power are achieved without sacrificing code performance. When slight performance degradation can be tolerated, the compiler uses profile feedback to realize an average of 51.7% static and 9.4% dynamic power reduction.
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A Low-Power Design of Motion Estimation Blocks for Low Bit-Rate Wireless Video Communications
… for video communications. We propose a low-power design of a motion estimation block for a low bit-rate video codec standard H.263. Since the motion estimation is computationally intensive to result in large power consumption, a low-power design is essential for portable or mobile systems. …
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Network lifetime extension, power conservation and interference suppression for next generation mobile wireless networks
… against undesired interference of unknown power, while preserving simple design, with closed-form solution for error probabilities. It is shown that these detectors are linearly optimal, if the interference power is unknown. In the area of network lifetime extension, a new approach to …
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K-hot pipelining
… domain now support techniques to trade off power and performance. Such techniques are used to enforce power and thermal constraints, manage power and thermal budgets and respond to temperature and aging. Unfortunately, many of the current techniques are limited in the dynamic range they …
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Steady state thermal hydraulic analysis of hydride fueled BWRs
… constraints, an estimate of the power reduction due to the application of neutronic constraints is also performed. This investigation, focused only on the "New Core" cases, is coupled with an increase of the thickness of the gap separating adjacent bundles from 2 to 5 mm. Under …
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Power Management Schemes for Ultra Low Power Biomedical Devices
Device power dissipation has grown exponentially due to the rapid transistor technology scaling and increased circuit complexity. Motivated by the ultra low power requirements of emerging implantable and wearable biomedical devices, novel power management schemes are presented in this thesis to …
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Architecture study of a 3D CMOS-NEM FPGA
… flow and a customized cycle-accurate mixed-level power/thermal simulator have been developed. It is shown that 3D stacking together with NEM devices achieves a 33.11% delay reduction, 29.19% power reduction, and 78.23% footprint reduction over the baseline simultaneously, with negligible …
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