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Showing 1 to 10 of 10 for “"Post-silicon validation"”.
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Protocol-directed trace signal selection for post-silicon validation
… using NoC (network-on-chip) communication, post-silicon validation has become an arduous task that consumes much of the development time of the product. The process of finding the root cause of bugs during post-silicon validation is very difficult because of the lack of observability of all …
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High quality functional coverage based trace signal selection for post-silicon validation
… impossible to capture all bugs during the pre-silicon verification phase; therefore, a small number of bugs escape after a chip is manufactured. Once a chip is manufactured, it is considered as a black box since internal observability is lost. To increase observability for post-silicon …
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Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test
Post-Silicon validation is playing an increasingly important role as more chips are failing in the functional mode due to either manufacturing defects escaped during scan-based tests or design bugs missed during pre-silicon validation. Critical to the diagnosis engineer is the ability to observe as …
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System-level trace signal selection for post-silicon debug using linear programming
… using NoC (network- on-chip) communication, post-silicon validation has become and arduous task that consumes much of the development time of the product. The process of finding the root cause of bugs found in post-silicon validation has proven to be much more difficult than in pre-silicon …
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Low-cost error detection through high-level synthesis
… has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a …
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Branch Guided Metrics for Functional and Gate-level Testing
… at different levels of abstraction such as post-silicon validation. Experimental results show that use of the new metric in our test generation framework can achieve a high level of branch and fault coverage for several benchmark circuits, while reducing the length of the vector sequence. …
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Robust and reliable hardware accelerator design through high-level synthesis
… has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a …
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Algorithms and Low Cost Architectures for Trace Buffer-Based Silicon Debug
An effective silicon debug technique uses a trace buffer to monitor and capture a portion of the circuit response during its functional, post-silicon operation. Due to the limited space of the available trace buffer, selection of the critical trace signals plays an important role in both minimizing …
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Scalable functional validation of next generation SoCs
… can cause loss of property or life. Hence, SoC validation is a crucial task to ensure the functional correctness of an SoC. The sheer size, presence of hundreds of concurrently executing heterogeneous IPs, vertical integration of SoC components e.g., hardware/firmware/software to realize …
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Sufficiency-based Filtering of Invariants for Sequential Equivalence Checking
Verification, as opposed to Testing and Post-Silicon Validation, is a critical step for Integrated Circuits (IC) Design, answering the question "Are we designing the right function?" before the chips are manufactured. One of the core areas of Verification is Equivalence Checking (EC), which is a …