Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 6 of 6 for “"Post-silicon debug"”.
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System-level trace signal selection for post-silicon debug using linear programming
… using NoC (network- on-chip) communication, post-silicon validation has become and arduous task that consumes much of the development time of the product. The process of finding the root cause of bugs found in post-silicon validation has proven to be much more difficult than in pre-silicon …
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Scalable functional validation of next generation SoCs
… challenges include observability enhancement and debug and diagnosis under the constraint of vertical integrations, identifying high-quality verification artifacts among others. In industrial practice, SoC validation is a manual, unsystematic, and ad hoc process that heavily relies on the …
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Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test
Post-Silicon validation is playing an increasingly important role as more chips are failing in the functional mode due to either manufacturing defects escaped during scan-based tests or design bugs missed during pre-silicon validation. Critical to the diagnosis engineer is the ability to observe as …
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Algorithms and Low Cost Architectures for Trace Buffer-Based Silicon Debug
An effective silicon debug technique uses a trace buffer to monitor and capture a portion of the circuit response during its functional, post-silicon operation. Due to the limited space of the available trace buffer, selection of the critical trace signals plays an important role in both minimizing …
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A truly embedded test structure for design-for-manufacturability, hardware security and VLSI testing
… in several contexts including defect detection, post-silicon debug and hardware-security. In this dissertation, I propose a high-precision and low-overhead embedded test structure, called REBEL, for measuring path delays in the circuit context. REBEL is minimally invasive to the design, as it …
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Robust and reliable hardware accelerator design through high-level synthesis
… stages in the hardware design and use cycle: pre-silicon debugging, post-silicon validation, and post-deployment error detection. Our solution for rapid pre-silicon debugging of accelerator designs is hybrid tracing: comparing a datapath-level trace of hardware execution with a reference software …