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Showing 1 to 2 of 2 for “"Pipelined SAR ADC"”.

  1. Design of residue amplifiers for high-speed pipelined-SAR ADCs

    … of a high-speed Gm-R residue amplifier used in a pipelined-SAR ADC, implemented in a 28nm CMOS process. The proposed design achieves good linearity and low gain variation due to temperature using a constant-gm biasing network. The thesis is organized as follows: Chapter 1 introduces the concepts …

    uiuc Repository record for Design of residue amplifiers for high-speed pipelined-SAR ADCs (opens in a new tab)

  2. A 1.7GS/s SAR ADC in 28nm CMOS

    This thesis presents a 1.7GS/s 9b single channel SAR ADC in 28nm CMOS technology. The main focus of the thesis is the leveraging of the pipelining, passive residue transfer, and partial interleaving techniques to increase sample rate of the ADC. The first chapter explains the motivation for …

    uiuc Repository record for A 1.7GS/s SAR ADC in 28nm CMOS (opens in a new tab)