Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 13 of 13 for “"Pipelined Architecture"”.
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Least-Squares Approximation and Polyphase Decomposition for Pipelining Recursive filters
… original circuit while seeking to construct a pipelined architecture. We present a technique that relaxes the need to preserve the exact frequency response and instead considers a least-squares formulation in conjunction with the pipelined architecture. The benefit of this design is that it …
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A low-complexity linear and iterative receiver architecture for multi-antenna communication systems
… design of low-complexity multi-antenna receiver architectures for communication networks and their demonstration in a real-time wireless environment. Our practical realization of an orthogonal frequency-division multi-antenna receiver is capable of several forms of linear and iterative detection. …
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Efficient design and implementation of image processing algorithms on reconfigurable hardware using Handel-C
… detection algorithms are implemented on FPGA. A pipelined architecture of these algorithms is presented. The proposed architectures are capable of producing one output on every clock cycle. The hardware modeling was accomplished using Handel-C (DK2 environment). The algorithm was tested on …
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3D backscatter localization for fine-grained robotics
… technical contributions. First, it presents a pipelined architecture that can extract a sensing bandwidth from every single backscatter packet that is three orders of magnitude larger than the backscatter communication bandwidth. Second, it introduces a Bayesian space-time superresolution …
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Heterogeneous CPU-FPGA system framework and scheduler
… on exploiting the multithreading of CPUs and the pipelined architecture of FPGAs. We specifically focus on the distribution of image processing tasks using the Canny edge detection algorithm as a representative test case to assess system performance under various workload conditions. Through a …
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A prototype parallel multi-FPGA accelerator for SPICE CMOS model evaluation
… area, and power. To this end, a multi-FPGA architecture is designed to exploit the inherent parallelism in the device model evaluation phase within the SPICE simulator. A code transformation flow which converts the high-level device model code to structural VHDL was also implemented. This …
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SCALABLE BUS ENCODING FOR ERROR-RESILIENT HIGH-SPEED ON-CHIP COMMUNICATION
… nature of the CODEC also simplifies use of pipelined architecture thereby improving the throughput of the bus.
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Enhancing Portability in High Performance Computing: Designing Fast Scientific Code with Longevity
… have little or no adverse impact on alternate architectures; this is done by implementing an iterative point solver requiring a high degree of data transfer bandwidth of a type commonly used in high performance applications used for computing a solution to partial differential equations (PDEs). …
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Knowledge intensive natural language generation with revision
… natural language generation systems use a pipelined architecture. Two problems with this architecture are poor task decomposition and the lack of interaction between conceptual and stylistic decisions making. A revision architecture operating in a knowledge intensive environment is proposed …
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Image watermarking, steganography, and morphological processing
… ones. The decomposition is suited for a parallel-pipelined architecture. The techniques can speed up the morphological processing and allow full freedom for users to design any type and any size of binary and grayscale structuring elements. In applications such as shortest path planning, a novel …
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Within-Die Delay Variation Measurement And Analysis For Emerging Technologies Using An Embedded Test Structure
… delays in a minimally invasive fashion; and its architecture measures the path delays more accurately. Design for manufacture-ability (DFM) analysis is done on the on 90 nm ASIC chips and 28nm Zynq 7000 series FPGA boards. I present ASIC results on within-die path delay variations in a …
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Novel load identification techniques and a steady state self-tuning prototype for switching mode power supplies
… FFT (CG-FFT).Hybrid CORDIC-LUT scalable architectures, has been introduced as alternative approach for the twiddle factors (phase factors) computation needed during the FFT algorithms execution. The shared core architecture uses a single phase rotator to satisfy all TF requests. It can …
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An Investigation of Methods to Improve Area and Performance of Hardware Implementations of a Lattice Based Cryptosystem
… for key exchanges, "NewHope." We describe a pipelined FPGA implementation of NewHope512cpa which dramatically increases the throughput for a similar design area. Our pipelined encryption implementation achieves 652.2 Mbps and a 0.088 Mbps/LUT throughput-to-area (TPA) ratio, which are the best …