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Showing 1 to 12 of 12 for “"Pipeline ADC"”.
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Equation-based hierarchical optimization of a pipeline ADC
… and hierarchical optimizations of a 10-stage pipeline ADC in a 0.18-um process. A pipeline ADC was chosen because it is a system small enough to be handled by a flat optimization, yet large enough to be approached with a hierarchical methodology. This allows a quantitative comparison of the …
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A sampling jitter tolerant continuous-time pipeline ADC
A sampling jitter tolerant continuous-time (CT) pipeline ADC has been presented in this thesis. In conventional discrete-time (DT) pipeline ADCs, the input is sampled upfront. The improvements in the bandwidth and sampling speed due to CMOS scaling have brought the deleterious effects of sampling …
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SHA-less pipeline ADC design with sampling clock skew calibration
The power efficiency of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the sampling clock skew between the sub-ADC and the multiplying digital-to-analog converter (MDAC) in …
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A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter
… systems require analog-to-digital converters (ADC) with a high dynamic range over a large digitization bandwidth (> 500 MHz). For high-speed high-resolution ADCs with an upfront sampler, the clock jitter poses a fundamental bottleneck for the maximum achievable signal-to-noise ratio (SNR). In …
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Feasibility of a 16bit, 3MSPS multibit per stage pipeline ADC using digital calibration
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science; and, Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.
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A Completely Integrated Warm-IF Receiver and a 10GS/s Analog-Delay Pipeline ADC for Radio-Telescope Applications
… technology. An analog-to-digital converter (ADC) was implemented, based on the design requirements of the SKA, in 65 nm CMOS technology. A novel method for LNA wide-band noise optimization is developed and implemented in 0.13 μm CMOS technology. The design of the LNA is verified …
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A reconfigurable analog-to-digital converter for a mobile receiver
… In terms of analog-to-digital converters (ADCs) of mobile terminal receivers, this indicates higher sample rate, lower power consumption and higher resolution. With comparison to other ADCs, the pipelined ADC architecture has most successfiilly covered the wide resolution limits and data …
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Comparator design and analysis for comparator-based switched-capacitor circuits
… known architectures. A prototype 1.5 b/stage pipeline ADC implemented in a 0.18 [mu]m CMOS process is presented that operates at 7.9 MHz, achieves 8.6 effective bits of accuracy, and consumes 2.5 mW of power. Techniques for the noise analysis of comparator-based systems are presented. …
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Design of a low power switched-capacitor pipeline analog-to-digital converter
<p>An Analog to Digital Converter (ADC) is a circuit which converts an analog signal into digital signal. Real world is analog, and the data processed by the computer or by other signal processing systems is digital. Therefore, the need for ADCs is obvious.</p><p>In this thesis, several novel …
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Oversampled pipline A/D converters with mismatch shaping
… a technique to improve the linearity of pipeline analog to digital converters (ADC). Through a combination of oversampling and mismatch shaping, the distortion introduced by component mismatch is modulated out of the input signal frequency band, where it can be removed by subsequent …
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Techniques for Reliable and Efficient Analog to Digital Conversion
Analog-to-Digital conversion (ADC) is an essential process in signal processing. It converts analog signals in the real world to digital codes that can be conveniently processed by digital systems. Among various ADC architectures, pipelined ADC is very attractive since it can achieve high …