Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 102 for “"Phase-locked loop"”.
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A phase-locked loop for laser scanners
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1984.
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Phase Noise in CMOS Phase-Locked Loop Circuits
Phase-locked loops (PLLs) have been widely used in mixed-signal integrated circuits. With the continuously increasing demand of market for high speed, low noise devices, PLLs are playing a more important role in communications. In this dissertation, phase noise and jitter performances are …
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Phase-locked loop using time-based integral control
… the time-based techniques in the context of phase-locked loop (PLL) implementation. Many studies of the topic have been performed in the past. Functioning as an effective replacement of passive capacitors, time-based integrators using oscillators prove to be more area efficient and highly …
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An optical phase locked loop for semiconductor lasers
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 1988.
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FPGA-based digital phase-locked loop analysis and implementation
The thesis presents a digital PLL project that will be used as an ECE 463 lab module and serve as a platform for future communication research projects. Field Programmable Gate Array (FPGA) technology is used for all digital signal processing tasks. A Direct Digital Synthesizer (DDS) is used to …
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Phase-locked loop digital FM receiver for wireless communications
Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
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Clock synthesizer design with analog and digital phase locked loop
… clocking circuit used in high-speed links is the Phase-Locked Loop (PLL). This thesis provides an in-depth analysis of basic analog PLL theory, architecture and transistor level design. The all-digital counterpart of the analog PLL will also be presented for its ultra low power and small …
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A 1.6-3.2GHz, high phase accuracy quadrature phase locked loop
… quadrature outputs, and is geared towards low phase noise. The VCO is identified as the limiting factor in the tuning range and source of the quadrature outputs, as well as the primary source of the phase noise above the loop bandwidth of the PLL, so its design is the principle focus herein. …
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A Novel Passive Islanding Detection Method Based on Phase-Locked Loop
… existing passive IDMs, and an analysis of the phase-locked loop (PLL) behaviour under grid-connected and islanded conditions using its quasi-static model. Based on the results of these studies, a novel passive IDM is developed that utilizes the PLL error to detect islanding with a small NDZ and …
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Low jitter phase-locked loop clock synthesis with wide locking range
… integration in many communications applications. Phase noise and timing jitter are important design considerations for these communications applications. The desire for highly complex levels of integration using low cost CMOS technologies works against the minimization of timing jitter and phase …
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A new programmable low noise all digital phase-locked loop architecture
… today almost without exception there are phase-locked loops (PLL) implemented within each system and often within each integrated circuit (IC). In fact, most PLL's are implemented monolithically within ICs without any or with very few external components. Additionally, most are implemented …
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Design of all digital phase-locked loop in serial link communication
… speed links, clocking circuitry is vital, and phase-locked loop (PLL) is at the heart of every on-chip clocking circuit. The clocking circuitry needs to be robust, low-power and fast in order to fulfill the increasing demand for high data rate links. The performance of the input/output (I/O) …
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A Fully Diff�erential Phase-Locked Loop With Reduced Loop Bandwidth Variation
Phase-Locked Loops (PLLs) are essential building blocks to wireless communications as they are responsible for implementing the frequency synthesizer within a wireless transceiver. In order to maintain the rapid pace of development thus far seen in wireless technology, the PLL must develop …
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An integer-N charge-pump phase-locked loop with controllable phase offset
In a phase-locked loop (PLL), the phase-offset is a result from non-idealities that usually need to be minimized to reduce the reference spurs at the output. However, in certain applications such as multi-buses, we would like to control this offset so we can align the clock with the data. This …
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A digital phase-locked loop for hard disk drive read channel appliations
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
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A low phase noise ring oscillator phase-locked loop for wireless applications
… of a 900MHz [Sigma][Detta] ring oscillator based phase-locked loop using 0.35[mu]m technology. Multiple phase noise theories are considered giving insight into low phase-noise voltage controlled oscillator design. The circuit utilizes a fully symmetric differential voltage controlled oscillator …
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Design and implementation of a phase locked loop for high-speed serial links
The student, Rushabh Mehta, accepted the attached license on 2016-04-25 at 13:40.
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Comparison of quadrature detector and phase-locked loop demodulator performance with LEOSAT applications
Continuous Phase Frequency Shift Keying (CPFSK) is a constant amplitude modulation of growing popularity in low earth orbit satellites (LEOSAT) because of its spectral efficiency. This thesis compares the error rate performance of CPFSK demodulation using quadrature detectors and phase-locked loops …
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Design of a phase locked loop based clocking circuit for high speed serial link applications
… to analysis and simulation of a charge-pump phase-locked loop based clocking circuit at both behavioral as well as transistor levels is presented for use as a synthesizer in a serial link. Finally, a survey of potential future research areas to explore for both PLLs in high-speed links as …
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