Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 32 for “"Phase-Locked Loops"”.
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Analysis and design of high order digital phase locked loops
The Phase Locked Loop (PLL) is an important component of many electronic devices; it can be employed as a frequency synthesizer, for clock data recovery, and as amplitude and frequency demodulators. It is an inherently nonlinear closed loop feedback system; the nonlinearity is due mainly to the …
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Dissertation review on a new control perspective on phase locked loops
The technique of phase-locked loop (PLL), an essential means for online frequency detection of incoming signal, which is widely used in our modern day communication system. PLL is traditionally viewed as a non-linear feedback control loop that will automatically locks the adjustable frequency of a …
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(VDL)² : a jitter measurement built-in self-test circuit for phase locked loops
… with the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital delay locked loop and a 60 stage Vernier delay line. This achieves a …
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Phase-Locked Loops, Islanding Detection and Microgrid Operation of Single-Phase Converter Systems
… of small-scale DER and ES systems at the single-phase (1Φ) distribution level to provide ancillary services such as peak load shaving, Static-VAr Compensation (STATCOM), ES, and Uninterruptable Power Supply (UPS) capabilities through the creation of microgrid systems. To interconnect DER and ES …
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Comparison of quadrature detector and phase-locked loop demodulator performance with LEOSAT applications
Continuous Phase Frequency Shift Keying (CPFSK) is a constant amplitude modulation of growing popularity in low earth orbit satellites (LEOSAT) because of its spectral efficiency. This thesis compares the error rate performance of CPFSK demodulation using quadrature detectors and phase-locked loops …
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Phase Noise in CMOS Phase-Locked Loop Circuits
Phase-locked loops (PLLs) have been widely used in mixed-signal integrated circuits. With the continuously increasing demand of market for high speed, low noise devices, PLLs are playing a more important role in communications. In this dissertation, phase noise and jitter performances are …
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Analysis of single event transients in arbitrary waveforms using statistical window analysis
… Complementary Metal-Oxide-Semiconductor (CMOS) phase-locked loops, and simulated transients in digital and analog circuits.The performance of the IRES filter in noisy environments shows that transients can be measured with higher fidelity than standard amplitude thresholding. This statistical …
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Automatic generation of an LC voltage controlled oscillator
… and is an integral part of circuits such as phase locked loops, frequency synthesizers, down conversion receivers, and clock generators. A typical design flow for a VCO involves architecture selection based on specification, calculation of circuit parameters, simulation, and iterations of …
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Simulation and Analysis of Behavioral Analog Systems
… such systems include power electronic circuits, phase-locked loops and RF circuits such as narrow-band amplifiers and mixers. The current trend towards integrating analog and digital components on a single chip has created a need for algorithms which can handle multiple components described at …
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Synchronization via correlated noise and automatic control in ecological systems
… in a robust way. This method is inspired by phase-locked loops and is based on a feedback loop with a differential control scheme, which allows to change the phases of the controlled systems. The effectiveness of the approach is demonstrated for controlled phase synchronization of regular …
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Time-Offset Fractional-N PLLs for Heterodyne FMCW SAR
… into the use of time-offset fractional-N phase locked loops (PLLs) for heterodyne frequency-modulated continuous-wave (FMCW) synthetic aperture radar (SAR) and the impact of spurii on such a system. Heterodyne receiver architectures avoid phenomena which limit the sensitivity of their …
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Techniques for low jitter clock multiplication
Phase realigning clock multipliers, such as Multiplying Delay-Locked Loops (MDLL), offer significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is achieved by introducing the reference signal directly into their voltage controlled oscillators (VCO) to realign the …
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Motion control and real-time systems: an approach to trajectory rebuilding in non-deterministic networks
… is analyzed and the proposed solution based on phase-locked loops adopted for the basic master-slave case has been improved to face with the other configurations.
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Analysis and Implementation of a Novel Single Channel Direction Finding Algorithm on a Software Radio Platform
… such as MUSIC [1][2] and ESPRIT use simultaneous phase information from each antenna to estimate the angle-of-arrival of the signal of interest. In many scenarios (e.g., hand-held systems), however, multiple receivers are impractical. Thus, single channel techniques are of interest, particularly …
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Design, Analysis and Experimental Evaluation of a Virtual Synchronous Machine Based Control Scheme for STATCOM Applications
… the shortcomings of conventional d-q frame phase-locked loops (PLL). In this dissertation, the VSM concept is extended by developing a STATCOM controller with it, which then behaves like a fully-adjustable synchronous condenser, including the adjustment of its "virtual" inertia and …
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A Fully Diff�erential Phase-Locked Loop With Reduced Loop Bandwidth Variation
Phase-Locked Loops (PLLs) are essential building blocks to wireless communications as they are responsible for implementing the frequency synthesizer within a wireless transceiver. In order to maintain the rapid pace of development thus far seen in wireless technology, the PLL must develop …
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Enabling Blocks for Integrated CMOS UWB Transceivers
… models for the simulation of chargepump phase-locked loops, namely the continuous time s-domain and discrete time z-domain approximations and the exact semi-analytical time-domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling …
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Synchronising coherent networked radar using low-cost GPS-disciplined oscillators
… further assesses the use of line-of-sight (LOS) phase compensation, where the direct sidelobe breakthrough is used as the phase reference, to improve the GPS-disciplined oscillator (GPSDO) synchronised bistatic Doppler performance. Coherent bistatic, multistatic, and networked radars require …
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A new programmable low noise all digital phase-locked loop architecture
… today almost without exception there are phase-locked loops (PLL) implemented within each system and often within each integrated circuit (IC). In fact, most PLL's are implemented monolithically within ICs without any or with very few external components. Additionally, most are implemented …
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