Global ETD Search
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Showing 1 to 13 of 13 for “"Phase locked loops (PLLs)"”.
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Time-Offset Fractional-N PLLs for Heterodyne FMCW SAR
… into the use of time-offset fractional-N phase locked loops (PLLs) for heterodyne frequency-modulated continuous-wave (FMCW) synthetic aperture radar (SAR) and the impact of spurii on such a system. Heterodyne receiver architectures avoid phenomena which limit the sensitivity of their …
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Analysis and Implementation of a Novel Single Channel Direction Finding Algorithm on a Software Radio Platform
… such as MUSIC [1][2] and ESPRIT use simultaneous phase information from each antenna to estimate the angle-of-arrival of the signal of interest. In many scenarios (e.g., hand-held systems), however, multiple receivers are impractical. Thus, single channel techniques are of interest, particularly …
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A Fully Diff�erential Phase-Locked Loop With Reduced Loop Bandwidth Variation
Phase-Locked Loops (PLLs) are essential building blocks to wireless communications as they are responsible for implementing the frequency synthesizer within a wireless transceiver. In order to maintain the rapid pace of development thus far seen in wireless technology, the PLL must develop …
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Phase Noise in CMOS Phase-Locked Loop Circuits
Phase-locked loops (PLLs) have been widely used in mixed-signal integrated circuits. With the continuously increasing demand of market for high speed, low noise devices, PLLs are playing a more important role in communications. In this dissertation, phase noise and jitter performances are …
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Synchronising coherent networked radar using low-cost GPS-disciplined oscillators
… further assesses the use of line-of-sight (LOS) phase compensation, where the direct sidelobe breakthrough is used as the phase reference, to improve the GPS-disciplined oscillator (GPSDO) synchronised bistatic Doppler performance. Coherent bistatic, multistatic, and networked radars require …
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Phase-Locked Loops, Islanding Detection and Microgrid Operation of Single-Phase Converter Systems
… of small-scale DER and ES systems at the single-phase (1Φ) distribution level to provide ancillary services such as peak load shaving, Static-VAr Compensation (STATCOM), ES, and Uninterruptable Power Supply (UPS) capabilities through the creation of microgrid systems. To interconnect DER and ES …
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Clock multiplication techniques for high-speed I/Os
… reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock …
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Interaction of additive and quantization noises in digital PLLs
Phase-locked loops (PLLs) are a crucial component in modern communications systems. Comprising of a phase-detector, linear filter, and controllable oscillator, they are widely used in radio receivers to retrieve the information content from remote signals. As such, they are capable of signal …
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Circuits for time-domain signal processing
… bandwidth limitation of conventional integer-N phase-locked loops (PLLs) by canceling the voltage controlled oscillator (VCO) noise in an open-loop fashion. Background calibration is presented to find the optimum gain for the noise cancellation path. Simulated in a 65nm CMOS process, the …
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Design of a phase locked loop based clocking circuit for high speed serial link applications
… a serial link, is presented. The fundamentals of PLLs are introduced and a complete guide to analysis and simulation of a charge-pump phase-locked loop based clocking circuit at both behavioral as well as transistor levels is presented for use as a synthesizer in a serial link. Finally, a survey …
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Lithium niobate RF-MEMS oscillators for IoT, 5G and beyond
… in series to the resonator. The measured best phase noise performances of the VCMO are -72 and -153 dBc/Hz at 1 kHz and 10 MHz offsets from 178.23 and 175.83 MHz carriers, respectively. The VCMO consumes a direct current (DC) of 60 µA from a 1.2 V supply while realizing a tuning range of 2.4 …
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Toward realizing power scalable and energy proportional high-speed wireline links
… LC-PLL based clock multi- plier. The phase locked loop (PLL) based multiplier was developed to overcome the limita- tions of the MDLL based approach. Proposed temperature compensated LC-PLL achieves power-on-lock in 1ns. The fifth and biggest contribution of this dissertation is the …
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Digital enhancement techniques for fractional-N frequency synthesizers
… first part of this work, a digital fractional-N phase locked loop (FNPLL) that employs a high resolution time-to-digital converter (TDC) and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter …