Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 23 for “"Phase Detector"”.
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False lock in sampled-data phase lock loops
The false lock characteristics of a sampled-data phase lock loop containing a phase detector with a sawtooth characteristic are investigated. The ideal processor of data operated on by such a phase detector nonlinearity is derived in open-loop form. A second system is proposed which is shown to …
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Low-Power CMOS Circuits for High-Performance Deep Submicron System on a Chip
… PLL-based clock multipliers. We propose a phase detector with reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problem of conventional DLL-based system.
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PLL-based active optical clock distribution
… This thesis analyzes the feasibility of a phase-locked loop (PLL) based approach to the optical-electrical clock signal conversion. The proposed small-signal current-steering optical-electrical phase detector extracts timing information from the optical reference without explicit …
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CMOS Receiver Design for Optical Communications over the Data-Rate of 20 Gb/s
… voltage. For the clock recovery circuit, a phase-locked loop is designed consisting of a frequency doubling mechanism, a mixer-based phase detector and a 40 GHz voltage-controlled oscillator. The proposed frequency doubling mechanism is an all-analog architecture instead of the conventional …
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High-Fidelity Power Injection From A Fuel Cell Onto A Variable-Frequency AC Power Bus
… batteries, and photovoltaics. In many cases, a phase detector determines the angle of the system which is used in the inverter control for the synchronization; however, there may be errors in the phase detection as a result of a trade-off between harmonic filtering and response time of the …
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Design and modelling of clock and data recovery integrated circuit in 130 nm CMOS technology for 10 Gb/s serial data communications
… and implementation of a fully monolithic 10 Gb/s phase and frequency-locked loop based clock and data recovery (PFLL-CDR) integrated circuit, as well as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The proposed …
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Supercritical Fluid Chromatography with Chemiluminescent Nitrogen and Sulfur Detection
The need for sensitive and selective detectors in supercritical fluid chromatography (SFC) is particularly evident since SFC can be used to analyze classes of compounds that are not readily amenable to either gas chromatography (GC) or liquid chromatography (LC). These compounds include species …
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5GHz CMOS resonant clock buffer with quadrature generation for fiber optic applications
… drive the clock inputs of a bang-bang half-rate phase detector in a 10GBit/sec Clock and Data Recovery Circuit. The 0.13um CMOS implementation shows significant power savings. A useful closed form expression for jitter transfer characteristic of generic linear-time-invariant filters is derived …
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Energy-efficient wireline transceivers
… clock and data recovery circuit (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency acquisition scheme based on bang-bang phase detector …
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A novel maximal-length sequence synchronisation network
… function with its maximum value at no code-phase offset. This allows for multiple access to a single resource and the suppression of multi-path interference as adjacent codes have little effect on each other. This same property requires that the receiver must accurately align its replica of …
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Design of a clock and data recovery circuit in 65 nm technology
… of the CDR is described. A CDR consists of a phase detector, a charge pump, a loop filter and a voltage-controlled oscillator. This thesis includes an overview of all the building blocks of a PLL-based CDR, derivation of the mathematical formulations of the negative feedback loop, and a report …
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Time-Offset Fractional-N PLLs for Heterodyne FMCW SAR
… into the use of time-offset fractional-N phase locked loops (PLLs) for heterodyne frequency-modulated continuous-wave (FMCW) synthetic aperture radar (SAR) and the impact of spurii on such a system. Heterodyne receiver architectures avoid phenomena which limit the sensitivity of their …
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Analysis and Treatment of Emerging Polar Contaminants
… system, hyphenated to a universal gas phase detector, flame ionization detector (FID), was designed. By using pure subcritical water as a mobile phase, temperature was used to control chromatographic retention. This instrument may be used for rapid screening of environmental samples …
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Time-based circuits for communication systems in advanced CMOS technology
… a [sigma][delta] modulator with a ring VCO and a phase detector, thereby implementing an A/D converter without traditional analog circuits. We also propose a single-slope A/D converter using time-to-digital conversion. By combining a few analog circuits and a ring oscillator based Time-to-Digital …
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A new programmable low noise all digital phase-locked loop architecture
… today almost without exception there are phase-locked loops (PLL) implemented within each system and often within each integrated circuit (IC). In fact, most PLL's are implemented monolithically within ICs without any or with very few external components. Additionally, most are implemented …
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Clock multiplication techniques for high-speed I/Os
… reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock …
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Interaction of additive and quantization noises in digital PLLs
Phase-locked loops (PLLs) are a crucial component in modern communications systems. Comprising of a phase-detector, linear filter, and controllable oscillator, they are widely used in radio receivers to retrieve the information content from remote signals. As such, they are capable of signal …
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Design of energy-efficient optical receiver
Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-12-01
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Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System
… Firstly, a low jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated using a dual path digital loop filter (DLF). In order to mitigate the phase jitter in the phase detector (PD), we implement the separate loop filter and the output is not affected by the …
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Three dimentional control of a diode based laser cutter
… at the high frequencies required for accurate phase shift measurements. A photodetector and phase shift measurement circuit was designed, simulated and constructed. The phase shift circuit amplified the signal from the light reflected off the workpiece and then compared that signal to a …
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