Global ETD Search

Functional timing analysis of VLSI circuits containing complex gates

Guntzel, Jose Luis Almada2000

… of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each combinational block of a circuit as a direct acyclic graph, which is used to estimate the critical delay. First timing …

brazil-ufrgs Repository record for Functional timing analysis of VLSI circuits containing complex gates (opens in a new tab)