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Showing 1 to 6 of 6 for “"Path Delay Faults"”.
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SCALABLE TEST GENERATION FOR PATH DELAY FAULTS
… design has drawn a lot of attention towards the path delay fault model (PDF) [1], which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes [2]. Path …
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Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests
… of digital integrated circuits increase rapidly, delay testing is indispensable to guarantee the correct timing behavior of the circuits. In this dissertation, we describe methods developed for three aspects of delay testing in scan-based circuits: test generation, path selection and built-in test …
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Static Learning for Problems in VLSI Test and Verification
… of sequentially untestable stuck-at faults, and (2) Equivalence checking of sequential circuits. Additionally, for the dissertation, we define a new concept called multi-cycle path delay faults (M-pdf) for latch based designs with multiple clock domains, and propose an …
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Behavioral delay fault modeling and test generation
… of operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation. In this work, a new behavioral …
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Search-space Aware Learning Techniques for Unbounded Model Checking and Path Delay Testing
… and Testing: Unbounded Model Checking and Path Delay Fault Testing, that commonly suffer from extremely large memory requirements. We propose efficient representations and intelligent learning techniques that reason on the problem structure and take advantage of the repeated search space, …
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Optimization Techniques for Performance and Power Dissipation in Test and Validation
… the sensitization characteristics of a path to be tested. The path delay fault models have been used for the purpose of studying this problem. Another important aspect in chip design is performance validation, which is increasingly perceived as the major bottleneck in integrated circuit …