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Showing 1 to 20 of 25 for “"Parallel hardware"”.

  1. Parallel hardware accelerated switch level fault simulation

    … paper presents a novel switch level extension to parallel fault simulation and the switch level circuit partitioning needed for parallel processing. The parallel switch level fault simulation technique uses 9-valued logic, N and P-type switch state tables, and a minimum operation in order to …

    vt Repository record for Parallel hardware accelerated switch level fault simulation (opens in a new tab)

  2. From Software Threads to Parallel Hardware with LegUp High-level Synthesis

    … (HLS) can automatically synthesize software to hardware. With the design specification in software, HLS can reduce the lengthy design cycles of hardware, and make the performance and energy-efficiency benefits of hardware accessible to those without hardware skills. Since the introduction of the …

    toronto-retro Repository record for From Software Threads to Parallel Hardware with LegUp High-level Synthesis (opens in a new tab)

  3. A transputer based parallel database system.

    … or the generated database applications. The Parallel-DB4GL (P-DB4GL) project represents an attempt to improve the performance of the generated database applications, by constructing a new concurrent implementation of DB4GL for execution on transputer-based parallel hardware. This thesis …

    sheffield-hallam Repository record for A transputer based parallel database system. (opens in a new tab)

  4. Rejection-Free and Partial Neighbor Search MCMC Algorithms

    … can be made more efficient through parallel hardware. However, for some specialized hardware, such as Digital Annealing Unit, the number of neighbors being considered at each step is limited. Hence, we propose an enhanced version of Rejection-Free known as Partial Neighbor Search, …

    toronto-retro Repository record for Rejection-Free and Partial Neighbor Search MCMC Algorithms (opens in a new tab)

  5. Bayesian inference algorithm on Raw

    This work explores the performance of Raw, a parallel hardware platform developed at MIT, running a Bayesian inference algorithm. Motivation for examining this parallel system is a growing interest in creating a self-learning and cognitive processor, which these hardware and software components can …

    mit Repository record for Bayesian inference algorithm on Raw (opens in a new tab)

  6. Efficient evaluation of functionally represented volumetric objects.

    … primitives within FRep and their suitability for parallelization. Furthermore, a new novel method is proposed to distribute FReps computational workloads on parallel hardware devices such as graphics programming units and multi-core processors.

    bournemouth Repository record for Efficient evaluation of functionally represented volumetric objects. (opens in a new tab)

  7. Heterogeneous parallel virtual machine: A portable program representation and compiler for performance and energy optimizations on heterogeneous parallel systems

    "Programming heterogeneous parallel systems, such as the SoCs (System-on-Chip) on mobile and edge devices is extremely difficult; the diverse parallel hardware they contain exposes vastly different hardware instruction sets, parallelism models and memory systems. Moreover, a wide range of diverse …

    uiuc Repository record for Heterogeneous parallel virtual machine: A portable program representation and compiler for performance and energy optimizations on heterogeneous parallel systems (opens in a new tab)

  8. Progress in Parallel Algorithms

    Parallel computing offers the promise of increased performance over sequential computing, and parallel algorithms are one of its key components. There has been no aggregated or generalized comparative analysis of parallel algorithms. In this thesis, we investigate this field as a whole. We aim to …

    mit Repository record for Progress in Parallel Algorithms (opens in a new tab)

  9. Runtime Verification and Debugging of Concurrent Software

    … power of multi-core processors and other parallel hardware keeps increasing, concurrent software that exploit these parallel computing hardware become crucial for achieving high performance. However, developing correct and efficient concurrent software is a difficult task for programmers …

    vt Repository record for Runtime Verification and Debugging of Concurrent Software (opens in a new tab)

  10. Searching for patterns in Conway's Game of Life

    … grid-based, all manipulations are embarrassingly parallel, allowing implementation on massively parallel hardware.

    cape-town Repository record for Searching for patterns in Conway's Game of Life (opens in a new tab)

  11. Cellular Automata: Algorithms and Applications

    … study because of their simplicity and inherently parallel operation. These characteristics make them a useful and efficient computation tool for applications such as cryptography and physical systems modelling, particularly when implemented on specialized parallel hardware. In this dissertation, …

    queens Repository record for Cellular Automata: Algorithms and Applications (opens in a new tab)

  12. Scheduling and synchronization for multicore concurrency platforms

    Developing correct and efficient parallel programs is difficult since programmers often have to manage low-level details like scheduling and synchronization explicitly. Recently, however, many hardware vendors have been shifting towards building multicore computers. This trend creates an enormous …

    mit Repository record for Scheduling and synchronization for multicore concurrency platforms (opens in a new tab)

  13. Early Vision Optimization: Parametric Models, Parallelization and Curvature

    … cuts and solving related problems on modern parallel hardware are developed and extensively evaluated. Finally, the thesis is concluded with two applications to early vision problems: heart segmentation and image registration.

    lund Repository record for Early Vision Optimization: Parametric Models, Parallelization and Curvature (opens in a new tab)

  14. Efficient Verifiable Computation Made Easy

    … a critical concern. Given the inherent data parallelism and heavy use of vector operations in ZKP computations, multicore CPUs and GPUs offer a promising acceleration path. Unfortunately, accelerated programming for ZKP remains challenging: ZKP algorithms evolve rapidly, their structures grow …

    mit Repository record for Efficient Verifiable Computation Made Easy (opens in a new tab)

  15. Accelerating the Jacobi Iteration for Solving Linear Systems of Equations using Theory, Machine Learning, and High Performance Computing

    … efficiently requires the use of massively parallel hardware with high computational throughput (such as GPUs), as well as the development of linear solver algorithms which respect the memory hierarchy of these hardware architectures to achieve the best performance. This thesis offers two …

    mit Repository record for Accelerating the Jacobi Iteration for Solving Linear Systems of Equations using Theory, Machine Learning, and High Performance Computing (opens in a new tab)

  16. Automatic Co-Synthesis of Hardware and Software Safety Monitors for Embedded Systems

    … and framework designed to automate synthesis of hardware and/or software monitors from pseudo- English statements. The automatic steps include translating English properties to formalisms, converting the formalisms into monitor automata, and formally verifying the monitors. GROOT addresses the …

    vt Repository record for Automatic Co-Synthesis of Hardware and Software Safety Monitors for Embedded Systems (opens in a new tab)

  17. Theory and design of a hardware stochastic reliability simulator.

    … systems requires fast simulation. Considerable parallel hardware operation is employed to produce simulation speeds faster than lOOyears/second, independent of the number of system components. A novel technique is also used to gain further speed via asynchronous time scaling. Modelling of …

    rgu Repository record for Theory and design of a hardware stochastic reliability simulator. (opens in a new tab)

  18. Hybrid STM/HTM for nested transactions in Java

    … for scaling concurrent programs running on parallel hardware. Software TM (STM) has the benefit of being able to run general transactional programs, but at the significant cost of overheads imposed to log memory accesses, mediate access conflicts, and maintain other transaction metadata. …

    purdue-thes Repository record for Hybrid STM/HTM for nested transactions in Java (opens in a new tab)

  19. Grid and high performance computing applied to bioinformatics

    … time have led to the use of distributed and parallel computing infrastructures for their analysis. In this context Grid computing has been successfully used. Grid computing is based on a distributed system which interconnects several computers and/or clusters to access global-scale resources. …

    cagliari Repository record for Grid and high performance computing applied to bioinformatics (opens in a new tab)

  20. Compilers for portable programming of heterogeneous parallel & approximate computing systems

    … a single system may include multiple different parallelism models, instruction sets, memory hierarchies, and systems use different combinations of these features. This is further complicated by software and hardware approximate computing optimizations. Different compute units on an SoC use …

    uiuc Repository record for Compilers for portable programming of heterogeneous parallel & approximate computing systems (opens in a new tab)

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