Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 16 of 16 for “"PCIe"”.
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Signal integrity diagnosis and distributed physical-based transmission line model development for PCIe 5.0 connector
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms
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PicoRF: A PC-based SDR Platform using a High Performance PCIe Plug-in Card Extension
… modified during run-time. Through a high speed PCIe connection, partial bitstreams can be downloaded from the host PC to the FPGA at a very high speed making it possible for the radio to modify its function in very short time intervals and greatly reducing the service interruption time. Control …
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Design and simulation of a PCI Express Gen 3.0 communication channel
PCI Express (PCIe) is a serial interconnect technology, developed by the PCI-Sig organization, which provides high bandwidth data transmission with the added benefits of reduced board space requirements, smaller connectors and simplified PCB layouts. Since faster and faster data rates are more …
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Exploitation from Malicious PCI Express Peripherals
… peripherals delivered over the PCI Express (PCIe) protocol. Malicious peripherals can be plugged directly into internal PCIe slots, or connected via an external Thunderbolt connection. To prove this thesis, we designed and built a new PCIe attack platform. We discovered that a simple platform …
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Cutting the datacenter tax in heterogeneous systems: a coherence-spectrum approach
… emerging coherent interconnect built on top of PCIe. We first provide a characterization of CXL Type-2 device and derive practical guidelines for its use. Applying these insights to the memory tax reduction, we reimplement two optimization features with coherent load/store semantics. Compared to …
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Demystifying CXL type-2 devices—with composable CXL-SSDS as a case study
CXL is a PCIe-based interconnect that defines three protocols for three classes of devices, each with distinct capabilities. Commercial adoption has arrived first for CXL Type-3 devices, with CXL Type-2 devices emerging afterward—making it timely to clarify CXL Type-2 device’s capabilities and …
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NUMA Data-Access Bandwidth Characterization and Modeling
… thesis a method for analyzing main memory and PCIe data-access characteristics of modern AMD and Intel NUMA architectures is presented. Also presented here is the synthesis of data-access performance models designed to quantify the effects of these architectural characteristics on data-access …
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A Dynamically Reconfigurable Parallel Processing Framework with Application to High-Performance Video Processing
… frames per second across an eight lane Gen I PCIe bus. Overall, optimal performance is achieved in the sense that video data is processed at the maximum possible rate that can be streamed through the processing cores. This performance, coupled with inherent ability to dynamically add new …
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A Neural Signal Processor for Low-Latency Spike Inference
… Peripheral Component Interconnect Express (PCIe) interface to the PC, producing the real-time spike trains. The real-time spike trains can be used for further processing, such as real-time decoding. Several types of ground-truth data, including intracellular/extracellular paired recordings, …
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Accelerated Storage Systems
… a way that minimizes data movement across the PCIe bus, while exposing data parallelism to maximize the potential for acceleration on the GPU. Our research aims to improve the overall reliability of a PFS by developing a distributed per-file parity generation that provides end-to-end data …
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Predictable and monitored execution for COTS-based real-time embedded systems
… almost 200% for a dual core system with a single PCIe peripheral. To overcome this issue, we propose both analysis techniques to compute upper bounds on the worst-case task delay, as well as hardware and software control abstractions to reduce such delay. In particular, we detail the design and …
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Heterogeneous system and application communication modeling
With the end of Dennard scaling, high-performance computing increasingly relies on heterogeneous systems with specialized hardware to improve application performance. This trend has driven up the complexity of high-performance software development, as developers must manage multiple programming …
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SdrLift: A Domain-Specific Intermediate Hardware Synthesis Framework for Prototyping Software-Defined Radios
… and Peripheral Component Interconnect Express (PCIe) bus. Gateware for programming FPGAs is described at a lowlevel of design abstraction using Register Transfer Language (RTL), typically using either VHSIC-HDL (VHDL) or Verilog code. In practice, the low-level description languages have a very …
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Popcorn Linux: A Compiler and Runtime for Execution Migration Between Heterogeneous-ISA Architectures
… via point-to-point interconnect over PCIe. This dissertation shows that sub-millisecond state transformation is achievable. Additionally, it shows that for a datacenter-like workload using benchmarks from the NAS Parallel Benchmark suite, the system can trade some performance for up to …
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Design and Analysis of a Real-time Data Monitoring Prototype for the LWA Radio Telescope
Increasing computing power has been helping researchers understand many complex scientific problems. Scientific computing helps to model and visualize complex processes such as molecular modelling, medical imaging, astrophysics and space exploration by processing large set of data streams collected …
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Code generation and runtime techniques for enabling data-efficient deep learning training on GPUs
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-03-28 without embargo terms