Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 9 of 9 for “"On-chip Interconnect"”.
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Equalized on-chip interconnect : modeling, analysis, and design
This thesis work explores the use of equalization techniques to improve throughput and reduce power consumption of on-chip interconnect. A theoretical model for an equalized on-chip interconnect is first suggested to provide mathematical formulation for the link behavior. Based on the model, a …
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VLSI Architectures for Iterative Channel Decoders
… LDPC codes introduce another complexity dimension related to the on-chip interconnect bottleneck of LDPC decoders. A new parameterized-core-based design methodology targeted for scalable and programmable LDPC decoders is proposed. The methodology solves the problems of excessive memory overhead, …
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Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs
Chip Multi-Processors(CMPs) have become mainstream in recent years, providing increased parallelism as core counts scale. While a tiled CMP is widely accepted to be a scalable architecture for the many-core era, on-chip cache organization and coherence are far from solved problems. As the on-chip …
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Efficient on-chip Network architectures for multicore VLSI systems.
Designing an efficient and flexible on-chip interconnect structure which can connect a large number of cores is an important issue since continued scaling of semiconductor technologies will enable an ever greater number of cores or processing elements (PEs) to be placed onto a chip. As a result, …
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On-Chip Network exploration and synthesis
… improves, the trend of processor designs has gone towards multi-core architectures. Networks-on-Chips (NoCs) have become popular on-chip interconnect fabrics that connect the ever-increasing cores because of their ability to provide high-bandwidth. However, as the number of cores keeps …
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SC²EPTON : high-performance and scalable, low-power and intelligent, ordered Mesh on-chip network
… to multicore processors, to the point where the on-chip interconnect plays a larger role in achieving the desired performance and power goals. Shared memory multicores are subject to data sharing concerns as each processor computes on data locally, and needs to be aware of accesses by other …
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Many-core architectures with time predictable execution Support for hard real-time applications
Hybrid control systems are a growing domain of application. They are pervasive and their complexity is increasing rapidly. Distributed control systems for future "Intelligent Grid" and renewable energy generation systems are demanding high-performance, hard real-time computation, and more …
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Interconnect design techniques for multicore and 3D Integrated circuits.
Over the past 40 years, the semiconductor industry has witnessed the exponential growth trend in system complexity as predicted by Moore’s law, facilitated by continuously shrinking transistor and wire dimensions. Three dimensional (3D) circuit technology, with multiple tiers of active devices …
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Software security challenges in the era of modern hardware
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-12-04 without embargo terms