Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 17 of 17 for “"On-Chip Network"”.
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On-Chip Network exploration and synthesis
… improves, the trend of processor designs has gone towards multi-core architectures. Networks-on-Chips (NoCs) have become popular on-chip interconnect fabrics that connect the ever-increasing cores because of their ability to provide high-bandwidth. However, as the number of cores keeps …
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Efficient on-chip Network architectures for multicore VLSI systems.
Designing an efficient and flexible on-chip interconnect structure which can connect a large number of cores is an important issue since continued scaling of semiconductor technologies will enable an ever greater number of cores or processing elements (PEs) to be placed onto a chip. As a result, …
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Balancing Performance, Area, and Power in an On-Chip Network
… become increasingly complex while design time continues to dwindle. As feature sizes shrink, wire resistance and delay increase, limiting architects from scaling designs centered around a single thread of execution. Where previous decades have focused on exploiting instruction-level parallelism, …
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SC²EPTON : high-performance and scalable, low-power and intelligent, ordered Mesh on-chip network
… to multicore processors, to the point where the on-chip interconnect plays a larger role in achieving the desired performance and power goals. Shared memory multicores are subject to data sharing concerns as each processor computes on data locally, and needs to be aware of accesses by other …
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On-chip networks for manycore architecture
… the past decade, increasing the number of cores on a single processor has successfully enabled continued improvements of computer performance. Further scaling these designs to tens and hundreds of cores, however, still presents a number of hard problems, such as scalability, power efficiency and …
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Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs
Chip Multi-Processors(CMPs) have become mainstream in recent years, providing increased parallelism as core counts scale. While a tiled CMP is widely accepted to be a scalable architecture for the many-core era, on-chip cache organization and coherence are far from solved problems. As the on-chip …
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Cache coherent commutative operations
… and evaluates its performance under simulation in zsim. MEUSI extends the MESI protocol to allow data to be cached in a new update-only state, reducing both block-level thrashing and on-chip network traffic under many parallel workflows. Coup permits both single-word and multi-word …
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Latency reduction techniques in chip multiprocessor cache systems
Single-chip multiprocessors (CMPs) solve several bottlenecks facing chip designers today. Compared to traditional superscalars, CMPs deliver higher performance at lower power for thread-parallel workloads. In this thesis, we consider tiled CMPs, a class of CMPs where each tile contains a slice of …
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Globally Synchronized Frames for guaranteed Quality-of-Service in shared memory systems
Resource contention among concurrent threads on multicore platforms results in greater performance variability of individual threads than traditionally seen with time-multiplexed threads on single-core platforms. This performance variability makes it hard to provide performance guarantees, degrades …
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Reducing data movement in multicore chips with computation and data co-scheduling
Energy efficiency is the main limitation to the performance of parallel systems. Current architectures often focus on making cores more efficient. However, data movement is much more costly than basic compute operations. For example, at 28 nm, a main memory access is 100x slower and consumes 1000x …
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Eliminating on-chip traffic waste: are we there yet?
As technology continues to scale, the memory hierarchy in processors is predicted to be a major component of the overall system energy budget. This has led many researchers into focusing on techniques that minimize the amount of data moved, and the distance that it is moved. While many techniques …
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Efficient hardware and software assist for many-core performance
… individual core has been lagged. It led application developers to extract more parallelism from a number of cores to make their applications run faster. However, writing a parallel program that scales well with the increasing core counts is challenging. Consequently, many parallel applications …
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Mitigating the Cost, Performance, and Power Overheads Induced by Load Variations in Multicore Cloud Servers
<p>Load variations whether in space or time pose a significant challenge to system designers. These load variations may induce inefficiencies such as load imbalance and over-provisioning, resulting in performance/power/cost overheads. The goal of my research is to mitigate such variation-induced …
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Architecture design for highly flexible and energy-efficient deep neural network accelerators
Deep neural networks (DNNs) are the backbone of modern artificial intelligence (AI). However, due to their high computational complexity and diverse shapes and sizes, dedicated accelerators that can achieve high performance and energy efficiency across a wide range of DNNs are critical for enabling …
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Methodologies, Architectures, and Prototypes for Scaling On- and Off-Chip Interconnects
… to embrace parallelism, both within single chips and across multiple compute devices, in order to meet the growing computational demands. Efficient data movement, both on-chip and off-chip, has thus become increasingly critical. However, scaling on- and off-chip interconnects each presents …
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Exploiting software information for an efficient memory hierarchy
Power consumption is one of the most important factors in the design of today’s processor chips. Multicore and heterogeneous systems have emerged to address the rising power concerns. Since the memory hierarchy is becoming one of the major consumers of the on-chip power budget in these systems, …
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Symmetric rearrangeable networks and algorithms
A class of symmetric rearrangeable nonblocking networks has been considered in this thesis. A particular focus of this thesis is on Benes networks built with 2 x 2 switching elements. Symmetric rearrangeable networks built with larger switching elements have also being considered. New applications …