Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 19 of 19 for “"Network-on-chip (NoC)"”.
-
Toward time-predictable execution of multi-task real-time systems
Guaranteeing time-predictable execution in real-time systems involves the management of not only processors but also other supportive components such as cache memory, network on chip (NoC), memory controllers. These three components are designed to improve the system computational throughput …
-
Application-aware deadlock-free oblivious routing
Systems that can be integrated on a single silicon die have become larger and increasingly complex, and wire designs as communication mechanisms for these systems on chip (SoC) have shown to be a limiting factor in their performance. As an approach to remove the limitation of communication and to …
-
Energy consumption in networks on chip : efficiency and scaling
… is increased by replicating processing cores on a chip rather than making CPUs larger and faster. This design strategy is motivated by the superior energy efficiency of the multi-core architecture compared to the traditional monolithic CPU. If the trend continues as expected, the number of …
-
Efficient on-chip Network architectures for multicore VLSI systems.
Designing an efficient and flexible on-chip interconnect structure which can connect a large number of cores is an important issue since continued scaling of semiconductor technologies will enable an ever greater number of cores or processing elements (PEs) to be placed onto a chip. As a result, …
-
Algorithms and low power hardware for keyword spotting
… devices to provide hands-free interface. It continuously listens to all sound signals, detects specific keywords and triggers the downstream system. The key design target of a KWS system is to achieve high classification accuracy of specified keywords and have low power consumption while doing …
-
Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip
Traditionally, the computing system security has been tackled as a software-level problem. With the globalization of the modern semiconductor industry, the design of a system may involve different parties, especially for the design of system-on-chip (SoC) where the high complexity of the design has …
-
Investigation into low power and reliable system-on-chip design
… likely that the demand for multiprocessor system-on-chip (MPSoC) with low power consumption and high reliability in the presence of soft errors will continue to increase. However, low power and reliable MPSoC design is challenging due to conflicting trade-off between power minimisation and …
-
Serialization and asynchronous techniques for reliable network-on-chip communication
The Network-on-Chip (NoC) paradigm has been proposed as a potentially viable onchip communication infrastructure for multiprocessor SoC. This thesis investigates the development and validation of efficient links that improve NoC performance, power consumption and reliability. There is emphasis on …
-
Towards low-power yet high-performance networks-on-chip
A network-on-chip (NoC), the de-facto communication backbone in manycore processors, consumes a significant portion of total chip power, competing against the computation cores for the limited power and thermal budget. On the other hand, overall system performance of manycore chips increasingly …
-
On Hardware Implementation of Discrete-Time Cellular Neural Networks
Cellular Neural Networks are characterized by simplicity of operation. The network consists of a large number of nonlinear processing units; called cells; that are equally spread in the space. Each cell has a simple function (sequence of multiply-add followed by a single discrimination) that takes …
-
Symmetric rearrangeable networks and algorithms
A class of symmetric rearrangeable nonblocking networks has been considered in this thesis. A particular focus of this thesis is on Benes networks built with 2 x 2 switching elements. Symmetric rearrangeable networks built with larger switching elements have also being considered. New applications …
-
Low Power Techniques for Future Network-on-Chip Architectures
In a multi-many/core system, the Network-on-Chip (NoC) based communication backbone is responsible for a relevant fraction of the overall energy budget. In fact, the I/O buffers, the crossbars of the routers and the inter-router links are the main contributors of the NoC s energy dissipation. …
-
System-level trace signal selection for post-silicon debug using linear programming
… complexity of modern digital designs using NoC (network- on-chip) communication, post-silicon validation has become and arduous task that consumes much of the development time of the product. The process of finding the root cause of bugs found in post-silicon validation has proven to be much …
-
Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche
The digital electronic market development is founded on the continuous reduction of the transistors size, to reduce area, power, cost and increase the computational performance of integrated circuits. This trend, known as technology scaling, is approaching the nanometer size. The lithographic …
-
Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs
<p>With the continuous scaling of transistors to smaller dimensions, it has now become feasible to pack billions of transistors in a single chip. However, interconnect does not scale as well as transistors; hence a significant amount of research is focused today on finding viable alternatives to …
-
Fine-grained Adaptivity for Dynamic On-chip Networks
A key challenge of building chip multiprocessors (CMPs) is providing an efficient communication infrastructure for their increasing communication demands. Networks-on-Chip (NoCs) offer a scalable, high-bandwidth, low-latency solution to this problem, but unfortunately incur significant area and …
-
Reconfigurable Computing Based on Commercial FPGAs. Solutions for the Design and Implementation of Partially Reconfigurable Systems = Computación reconfigurable basada en FPGAs comerciales. Soluciones para el diseño e implementación de sistemas parcialmente reconfigurables.
… el campo de investigación de la computación reconfigurable. Este campo ha experimentado un crecimiento abrumador en los últimos años como resultado de la evolución de los dispositivos reconfigurables, donde las Field Programmable Gate Arrays (FPGAs) son el máximo exponente desde el punto de …