Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 43 for “"Network-on-chip"”.
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A directory enhanced network on chip for FPGA
… presents and evaluates a directory enhanced network on chip for FPGA, with the goal of improving the performance of cores generated by FCUDA, a translation tool enabling CUDA code to be run on FGPAs. NoCs are an inherently scalable platform, as aggregate system bandwidth increases with the …
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Low Power Techniques for Future Network-on-Chip Architectures
In a multi-many/core system, the Network-on-Chip (NoC) based communication backbone is responsible for a relevant fraction of the overall energy budget. In fact, the I/O buffers, the crossbars of the routers and the inter-router links are the main contributors of the NoC s energy dissipation. …
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Heterogeneous prioritization for network-on-chip based multi-core systems
In chip multi-processor (CMP) systems, communication and memory access both play an important role in influencing the performance achievable by the system. The manner in which the network packets (on-chip cache requests/responses) and off-chip memory bound packets are handled, in multi-core …
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Runtime Detection of Hardware Trojan in Untrusted Network-on-Chip
Traditionally, the computing system security has been tackled as a software-level problem. With the globalization of the modern semiconductor industry, the design of a system may involve different parties, especially for the design of system-on-chip (SoC) where the high complexity of the design has …
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Carbon nanotubes as interconnect for next generation network on chip
… with their single-core equivalent. Recently, Networks-on-Chip (NoC) have emerged as a communication methodology for multi core chips. Network-on-Chip uses packet based communication for establishing a communication path between multiple cores connected via interconnects. Clock frequency, …
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Serialization and asynchronous techniques for reliable network-on-chip communication
The Network-on-Chip (NoC) paradigm has been proposed as a potentially viable onchip communication infrastructure for multiprocessor SoC. This thesis investigates the development and validation of efficient links that improve NoC performance, power consumption and reliability. There is emphasis on …
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Network-on-chip design for a chiplet-based waferscale processor
… learning and big data analysis, processors continue to increase in area and incorporate more computational cores. This growth requires innovation in manufacturing processes to build larger systems, and architectural changes to enable performance to scale acceptably. One significant …
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Fuzzy-token: An adaptive Mac protocol for wireless network-on-chip
… than a thousand processor cores within a single chip. In this context, as parallel programs continue to increase the amount of data sharing and signaling between cores, on-chip communication becomes a critical issue. Unfortunately, traditional on-chip networks have been proven to not scale well …
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Enabling dedicated single-cycle connections over a shared network-on-chip
Adding multiple processing cores on the same chip has become the de facto design choice as we continue extracting more and more performance/watt from our chips in every technology generation. In this context, the interconnect fabric connecting the cores starts gaining paramount importance. A high …
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Design and Performance Evaluation of Network-on-Chip Communication Protocols and Architectures
… down of transistor technology allows microelectronics manufacturers such as Intel and IBM to build always more sophisticated systems on a single microchip. The classical interconnection solutions based on shared buses or direct connections between the modules of the chip are becoming obsolete as …
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SDNoC 42: modelo de SDNoC baseada em otimização de caminhos mínimos
In this work, we developed a new network-on-chip architecture using softwaredefined networks; this architecture proved to be robust and capable of improving routing in a network-on-chip. The implementation consists of a software-defined network-on-chip architectural model, exploring the parallelism …
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Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs
Chip Multi-Processors(CMPs) have become mainstream in recent years, providing increased parallelism as core counts scale. While a tiled CMP is widely accepted to be a scalable architecture for the many-core era, on-chip cache organization and coherence are far from solved problems. As the on-chip …
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Toward time-predictable execution of multi-task real-time systems
Guaranteeing time-predictable execution in real-time systems involves the management of not only processors but also other supportive components such as cache memory, network on chip (NoC), memory controllers. These three components are designed to improve the system computational throughput …
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Overcoming nanoscale variations through statistical error compensation
Increasingly severe parameter variations that are observed in advanced nanoscale technologies create great obstacles in designing high-performance, next-generation digital integrated circuits (ICs). Conventional design principles impose increased design margins in power supply, device sizing, and …
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Reverse Engineering the Intel Cascade Lake Mesh Interconnect
… processors have driven the move to more scalable on-chip networks to allow for efficient communication between the cores, memory subsystem, and other processor peripherals. Intel’s latest line of Scalable processors introduced the mesh interconnect in the form of a two-dimensional network of rings …
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Application-aware deadlock-free oblivious routing
Systems that can be integrated on a single silicon die have become larger and increasingly complex, and wire designs as communication mechanisms for these systems on chip (SoC) have shown to be a limiting factor in their performance. As an approach to remove the limitation of communication and to …
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