Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 3 of 3 for “"Multiplying delay locked loop (MDLL)"”.
-
Toward realizing power scalable and energy proportional high-speed wireline links
… LC-PLL based clock multi- plier. The phase locked loop (PLL) based multiplier was developed to overcome the limita- tions of the MDLL based approach. Proposed temperature compensated LC-PLL achieves power-on-lock in 1ns. The fifth and biggest contribution of this dissertation is the design …
-
Design of energy efficient high speed I/O interfaces
The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.
-
Dynamic power management for computing and communication
Power management is essential in state-of-the-art many-core processor and system-on-chip designs due to the ever-increasing demand for performance and the diminishing benefits from technology scaling. With more and more integration of processing cores and functional blocks, aggressive power …