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Showing 1 to 20 of 22 for “"Multi-core architectures"”.

  1. Modeling and scheduling heterogeneous multi-core architectures

    … kunnen worden. In dit doctoraatswerk werd het Multi-Program Performance Model (MPPM) ontwikkeld, een innovatief alternatief voor traditionele simulatie, dat het mogelijk maakt om tot 100.000x sneller een processorconfiguratie te evalueren. MPPM laat ons toe om nooit geziene exploraties te doen. …

    ghent Repository record for Modeling and scheduling heterogeneous multi-core architectures (opens in a new tab)

  2. Accelerated cooperative co-evolution on multi-core architectures

    … using the Go programming language. Go is a multi-core programming language with first-class constructs, channels and goroutines, that make it well suited to parallel programming. Our study focuses on Enforced Subpopulations (ESP) for single-agent systems and Multi-Agent ESP for multi-agent …

    cape-town Repository record for Accelerated cooperative co-evolution on multi-core architectures (opens in a new tab)

  3. Application Interference in Multi-Core Architectures: Analysis and Effects

    Clouds are an irreplaceable part of many business applications. They provide tremendous flexibility and gave birth for many related technologies – Software as a Service (SaaS) and the like. One of the biggest powers of clouds is load redistribution for scaling up and down on demand. This helps …

    trento Repository record for Application Interference in Multi-Core Architectures: Analysis and Effects (opens in a new tab)

  4. ARCHITECTURE-AWARE HARD-REAL-TIME SCHEDULING ON MULTI-CORE ARCHITECTURES

    … discourages this solution. This leads us to use multi-core architectures. Due to the same reason, real-time systems are also migrating from single-core towards multi-core systems. While multi-core systems provide scalable high computational power, they also expose real-time systems to several …

    siu-theses Repository record for ARCHITECTURE-AWARE HARD-REAL-TIME SCHEDULING ON MULTI-CORE ARCHITECTURES (opens in a new tab)

  5. Parallelization of hybrid multi-objective evolutionary algorithm on multi-core architectures

    Many real world optimization problems involve multiple conflicting objectives, constraints and parameters. Multi-objective optimization (MOO) techniques are used to solve these problems. The goal of MOO is to find a set of optimal solutions, or the Pareto optimal front. Multi-objective evolutionary …

    manitoba Repository record for Parallelization of hybrid multi-objective evolutionary algorithm on multi-core architectures (opens in a new tab)

  6. Autonomic behavioural framework for structural parallelism over heterogeneous multi-core systems.

    … exploit the latest developments in heterogeneous multi-core/many-core architectures. Structural programming paradigms propose a viable solution for e ciently programming modern heterogeneous multi-core architectures equipped with one or more programmable Graphics Processing Units (GPUs). Applying …

    rgu Repository record for Autonomic behavioural framework for structural parallelism over heterogeneous multi-core systems. (opens in a new tab)

  7. GePSeA: A General-Purpose Software Acceleration Framework for Lightweight Task Offloading

    … a small fraction of the computational power on multi-core architectures to offload complex application-specific tasks. Specifically, GePSeA provides a lightweight process that acts as a helper agent to the application by executing application-specific tasks asynchronously and efficiently. GePSeA …

    vt Repository record for GePSeA: A General-Purpose Software Acceleration Framework for Lightweight Task Offloading (opens in a new tab)

  8. ARCHITECTURE-AWARE MAPPING AND SCHEDULING OF MIXED-CRITICALITY APPLICATIONS ON MULTI-CORE PLATFORMS

    … budgets, the industry has begun a shift to multi-core architectures even in the embedded systems domain. Embedded real-time applications such as Avionics and Automotive systems are no exception to this trend. Such systems have strict certification requirements of subsets of their …

    siu-theses Repository record for ARCHITECTURE-AWARE MAPPING AND SCHEDULING OF MIXED-CRITICALITY APPLICATIONS ON MULTI-CORE PLATFORMS (opens in a new tab)

  9. Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies

    The new generations of multi-core chipset architectures achieve unprecedented levels of computational power while respecting physical and economical constraints. The cost of this power is bewildering program complexity. Atmospheric modeling is a grand-challenge problem that could make good use of …

    vt Repository record for Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies (opens in a new tab)

  10. Aperiodic Job Handling in Cache-Based Real-Time Systems

    … we extend the Cache Delay Server concept to multi-core architectures and propose approaches to schedule aperiodic jobs on appropriate Cache Delay Servers. Simulation results demonstrate the effectiveness of all our proposed algorithms in improving aperiodic job response times while …

    siu-theses Repository record for Aperiodic Job Handling in Cache-Based Real-Time Systems (opens in a new tab)

  11. On-Chip Network exploration and synthesis

    … the trend of processor designs has gone towards multi-core architectures. Networks-on-Chips (NoCs) have become popular on-chip interconnect fabrics that connect the ever-increasing cores because of their ability to provide high-bandwidth. However, as the number of cores keeps increasing, the …

    mit Repository record for On-Chip Network exploration and synthesis (opens in a new tab)

  12. SCA-Resistant and High-Performance Embedded Cryptography Using Instruction Set Extensions and Multi-Core Processors

    … These solutions make use of two state-of-the-art architectures of embedded processors: instruction set extensions and multi-core architectures. We show that, with proper processor micro-architecture design and suitable software programming, we are able to deliver SCA-resistant software which …

    vt Repository record for SCA-Resistant and High-Performance Embedded Cryptography Using Instruction Set Extensions and Multi-Core Processors (opens in a new tab)

  13. Convolutional neural networks and photonic crystals for particle identification at high energy collider experiments

    … in the LHCb computing infrastructure towards multi-core architectures provide the opportunity to benefit from the quickly evolving field of machine learning. The calculations of the presented neural network are well suited for quasi- real-time reconstruction through parallel processing. It …

    cambridge Repository record for Convolutional neural networks and photonic crystals for particle identification at high energy collider experiments (opens in a new tab)

  14. Modeling and evaluation of multi-core multithreading processor architectures in SystemC

    … focus. Rather then focusing on single-threaded architectures, designers have increasingly sought to improve system performance and increase overall throughput by exploiting thread-level parallelism through multithreaded multi-core architectures. Software modeling and simulation are common …

    queens Repository record for Modeling and evaluation of multi-core multithreading processor architectures in SystemC (opens in a new tab)

  15. Electro-Thermal Codesign in Liquid Cooled 3D ICs: Pushing the Power-Performance Limits

    … in CPU power dissipation due to advanced multi-core architectures and 3D integration technologies. Nowadays the problems of increased chip power density, leakage power and system temperatures have become major obstacles for further improvement in chip performance. The conventional air …

    maryland Repository record for Electro-Thermal Codesign in Liquid Cooled 3D ICs: Pushing the Power-Performance Limits (opens in a new tab)

  16. Next-generation safety-critical systems on multi-core platforms

    Multi-core platforms represent the answer of the industry to the increasing demand for computational capabilities. In fact, multi-core platforms can deliver large computational power together with minimum costs, compact size, weight and power usage. Multi-core architectures however are shaking the …

    uiuc Repository record for Next-generation safety-critical systems on multi-core platforms (opens in a new tab)

  17. Design and demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications

    … technology node. This has forced a move toward multi-core architectures, but the energy efficiency benefits of parallelism are limited by the sub-thresahold leakage and the minimum energy point for a given function. Avoiding this roadblock requires an alternative device with more ideal switching …

    mit Repository record for Design and demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications (opens in a new tab)

  18. Data-Driven Programming Abstractions and Optimization for Multi-Core Platforms

    Multi-core platforms have spread to all corners of the computing industry, and trends in design and power indicate that the shift to multi-core will become even wider-spread in the future. As the number of cores on a chip rises, the complexity of memory systems and on-chip interconnects increases …

    columbia-diss Repository record for Data-Driven Programming Abstractions and Optimization for Multi-Core Platforms (opens in a new tab)

  19. Using program behaviour to exploit heterogeneous multi-core processors

    Multi-core CPU architectures have become prevalent in recent years. A number of multi-core CPUs consist of not only multiple processing cores, but multiple different types of processing cores, each with different capabilities and specialisations. These heterogeneous multi-core architectures (HMAs) …

    glasgow Repository record for Using program behaviour to exploit heterogeneous multi-core processors (opens in a new tab)

  20. Designing, Modeling, and Optimizing Transactional Data Structures

    … as a promising synchronization abstraction for multi-core architectures. Unlike traditional lock-based approaches, TM shifts the burden of implementing threads synchronization from the programmer to an underlying framework using hardware (HTM) and/or software (STM) components. Although TM can be …

    vt Repository record for Designing, Modeling, and Optimizing Transactional Data Structures (opens in a new tab)

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