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Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.

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Showing 1 to 20 of 90 for “"Microarchitecture"”.

  1. Evaluating the security of novel microarchitecture

    Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2023-04-12 without embargo terms

    uiuc Repository record for Evaluating the security of novel microarchitecture (opens in a new tab)

  2. Superscalar processors via automatic microarchitecture transformations

    Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.

    mit Repository record for Superscalar processors via automatic microarchitecture transformations (opens in a new tab)

  3. A system for microarchitecture and logic optimization

    … netlists. Thus optimization is performed on the microarchitecture design and at a lower level for individual microarchitecture components.

    uiuc Repository record for A system for microarchitecture and logic optimization (opens in a new tab)

  4. Towards Using Free Memory to Improve Microarchitecture Performance

    … CPU-OS codesign. This can enable many new microarchitecture techniques that transparently leverage unused memory locations to help improve microarchitecture performance. We refer to these techniques as Free-memory-aware Microarchitecture Techniques (FMTs). In the context of HPC systems, we …

    vt Repository record for Towards Using Free Memory to Improve Microarchitecture Performance (opens in a new tab)

  5. Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots

    Computer architects rely heavily on software simulation to evaluate, refine, and validate new designs before they are implemented. However, simulation time continues to increase as computers become more complex and multicore designs become more common. This thesis investigates software structures …

    mit Repository record for Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots (opens in a new tab)

  6. Graph-based microarchitecture exploration: Automated optimization on RISC-V hardware

    Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2025-10-19 without embargo terms

    uiuc Repository record for Graph-based microarchitecture exploration: Automated optimization on RISC-V hardware (opens in a new tab)

  7. The role of microarchitecture in the tensile properties of polymer scaffolds

    … have a multiscale organisation, and their microarchitecture is at the origin of their mechanical properties. In particular, the protein collagen, providing the scaffold of the extracellular matrix, is responsible for soft tissue tensile strength, and its organisation directs the tensile …

    cambridge Repository record for The role of microarchitecture in the tensile properties of polymer scaffolds (opens in a new tab)

  8. Microarchitecture Categorization and Pre-RTL Analytical Modeling for Sparse Tensor Accelerators

    Specialized microarchitectures for exploiting sparsity have been critical to the design of sparse tensor accelerators. Sparseloop introduced the Sparse Acceleration Fea­ture (SAF) abstraction, which unifies prior work on sparse tensor accelerators into a taxonomy of sparsity optimizations. …

    mit Repository record for Microarchitecture Categorization and Pre-RTL Analytical Modeling for Sparse Tensor Accelerators (opens in a new tab)

  9. MICROARCHITECTURE OF A HIGH THROUGHPUT TEXTURE MAPPING PROCESSOR FOR INTERACTIVE 3D GRAPHICS

    … is limited to the detailed description of the microarchitecture and implementation of a texture address processor which interpolates texture addresses (texture coordinates), called the S, T and Q parameters, with perspective correction or without correction. The processor uses digital …

    nus Repository record for MICROARCHITECTURE OF A HIGH THROUGHPUT TEXTURE MAPPING PROCESSOR FOR INTERACTIVE 3D GRAPHICS (opens in a new tab)

  10. ASSESSMENT OF PERI-IMPLANT BONE MICROARCHITECTURE IN D4 BONE: AN EX VIVO MICROCT ANALYSIS

    … stability quotient (ISQ), and peri-implant bone microarchitecture in low-density bone (D4). The investigation focused on three Straumann implant systems: Bone Level Tapered (BLT), Bone Level X (BLX), and Tissue Level (TL). Materials and Methods: An ex vivo model utilizing porcine tibia bone was …

    temple Repository record for ASSESSMENT OF PERI-IMPLANT BONE MICROARCHITECTURE IN D4 BONE: AN EX VIVO MICROCT ANALYSIS (opens in a new tab)

  11. Towards Understanding Nanoparticle Uptake by the Liver: The Role of Flow Dynamics, Organ Microarchitecture and Cellular Phenotype

    … methods, we show that blood flow dynamics, organ microarchitecture and cellular phenotype govern the off-target accumulation of nanoparticles. These results suggest new strategies to improve nanoparticle delivery and in Aim 3 we demonstrate that manipulation of these factors can reduce quantum dot …

    toronto-retro Repository record for Towards Understanding Nanoparticle Uptake by the Liver: The Role of Flow Dynamics, Organ Microarchitecture and Cellular Phenotype (opens in a new tab)

  12. Using finite element models under multiple loading conditions to improve the association between radius and tibia microarchitecture and prevalent osteoporotic vertebral fracture

    Bone microarchitecture differences at the tibia and radius, measurable by high-resolution peripheral quantitative computed tomography (HR-pQCT) exist between individuals with a prevalent vertebral fracture and healthy controls. As fracture is a result of mechanical failure, FE models of these sites …

    calgary Repository record for Using finite element models under multiple loading conditions to improve the association between radius and tibia microarchitecture and prevalent osteoporotic vertebral fracture (opens in a new tab)

  13. Simplified vector-thread architectures for flexible and efficient data-parallel accelerators

    … is based on simplifying the instruction set, microarchitecture, and programming methodology for a vector-thread architecture. The thesis begins by categorizing regular and irregular data-level parallelism (DLP), before presenting several architectural design patterns for data-parallel …

    mit Repository record for Simplified vector-thread architectures for flexible and efficient data-parallel accelerators (opens in a new tab)

  14. The effect of continuous infusion of human parathyroid hormone on bone architecture in female mice

    … content (BMC), trabecular and cortical bone microarchitecture, and serum calcium levels were measured. There were no significant differences in BMD or BMC in either study in mice infused with either dosage, nor were there significant differences in femoral cortical bone microarchitecture. …

    mit Repository record for The effect of continuous infusion of human parathyroid hormone on bone architecture in female mice (opens in a new tab)

  15. Cross-layer instruction-aware timing error mitigation & evaluation for energy-efficient dependable architectures

    … across the layers of the application, microarchitecture and circuit. Accordingly, this thesis investigates cross-layer methods to mitigate, evaluate and model timing errors, exploiting the data-dependent timing behaviour of pipelined designs. In the first part of this thesis, techniques …

    qu-belfast Repository record for Cross-layer instruction-aware timing error mitigation & evaluation for energy-efficient dependable architectures (opens in a new tab)

  16. Discovering Novel Microarchitectural Security Vulnerabilities in Modern Processors

    … by leveraging the behavior of the CPU’s microarchitecture. I will present multiple proof-of-concept attacks showing PACMAN defeating Pointer Authentication on the Apple M1 SoC, the world’s first desktop processor that supports Pointer Authentication. I will also document the tools I have …

    mit Repository record for Discovering Novel Microarchitectural Security Vulnerabilities in Modern Processors (opens in a new tab)

  17. Analysis of the microarchitecutre of the human femoral head using micro-computertomography

    … heads from cadaveric donors and investigate the microarchitecture within each femoral head comprehensively. MATERIAL AND METHODS: Ten proximal femora was harvested from eight human cadaveric donors and these specimens were scanned using micro-computed tomography. Reconstructed batches of images …

    ajou Repository record for Analysis of the microarchitecutre of the human femoral head using micro-computertomography (opens in a new tab)

  18. Hormonal regulation of bone health: novel understandings of xenoestrogens and estrogen receptor-[alpha]

    … geometry, but improved measures of trabecular microarchitecture, implying differential roles for ER[alpha] in different bone compartments. We also found that ERKO could lead to increased expression of sclerostin, a bone growth inhibitor, in aged, male mice. In younger, male ERKO mice we found …

    missouri Repository record for Hormonal regulation of bone health: novel understandings of xenoestrogens and estrogen receptor-[alpha] (opens in a new tab)

  19. Techniques to Mitigate the Effects of Congenital Faults in Processors

    … we introduce a novel framework that shows how microarchitecture techniques can mitigate variation-induced errors and even trade them off for power and processor frequency. Several such techniques are analyzed---in particular, a high-dimensional dynamic-adaptation technique that maximizes …

    uiuc Repository record for Techniques to Mitigate the Effects of Congenital Faults in Processors (opens in a new tab)

  20. Efficient spatial and temporal safety for microcontrollers and application-class processors

    … (CHERI) secure capabilities for RISC-V microarchitectures. This includes implementations for three different scales of core, including microcontrollers and the first open application of CHERI to a superscalar processor. Tradeoffs in developing the architecture and performant …

    cambridge Repository record for Efficient spatial and temporal safety for microcontrollers and application-class processors (opens in a new tab)

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