Global ETD Search

Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.

Results

Showing 1 to 6 of 6 for “"MicroBlaze"”.

  1. FPGA Implementation of Blob Recognition

    … complex instructions by an integrated 32-bit CPU Microblaze. Each IP is tailored specifically to meet the needs of the application and at the same time to consume the minimum FPGA logic resources. Integrating both hardware and software on a single FPGA chip, this system can achieve the real-time …

    windsor Repository record for FPGA Implementation of Blob Recognition (opens in a new tab)

  2. Hardware/Software Co-Design Architecture and Implementations of MIMO Decoders on FPGA

    … with the preprocessing part on embedded MicroBlaze soft processor and the decoding part on customized hardware. The decoders for a 4 by 4 MIMO system with 16-QAM modulation scheme are prototyped on a Xilinx XC2VP30 FPGA device. The hardware implementations of the AV and VB decoders show …

    uno Repository record for Hardware/Software Co-Design Architecture and Implementations of MIMO Decoders on FPGA (opens in a new tab)

  3. Vector support for multicore processors with major emphasis on configurable multiprocessors

    … unit are presented for FPGA prototyping. The MicroBlaze processor, which is a commercial IP (Intellectual Property) core from Xilinx, is used as the scalar processor; in the experiments the vector unit is connected to a pair of MicroBlaze processors through standard bus interfaces. The overall …

    njit Repository record for Vector support for multicore processors with major emphasis on configurable multiprocessors (opens in a new tab)

  4. High-speed dynamic partial reconfiguration for field programmable gate arrays

    … on Virtex-4, (ii) a second targeting the Soft IP MicroBlaze on Virtex-5, (iii) a third targeting the Hard IP PowerPC440 on Virtex-5, and (iv) a fourth system targets the Hard IP PowerPC440 on Virtex-5 capable of adaptive feedback. The adaptive feedback Virtex-5 system can use internal voltage and …

    unm Repository record for High-speed dynamic partial reconfiguration for field programmable gate arrays (opens in a new tab)

  5. Radiation management, avionics development, and integrated testing of a Class-D space-based asteroid X-ray spectrometer

    … Xilinx and Actel FPGAs, and a softcore MicroBlaze processor. Although the REXIS instrument is classified as a high-risk Class-D project by NASA, it must safely interface (in the manner of "do no harm") with the low-risk Class-B OSIRIS-REx spacecraft. Furthermore, REXIS must operate in …

    mit Repository record for Radiation management, avionics development, and integrated testing of a Class-D space-based asteroid X-ray spectrometer (opens in a new tab)

  6. Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems

    Unmanned Aerial Systems (UAS) are aircraft without a human pilot on board. They are comprised of a ground-based autonomous or human operated control system, an unmanned aerial vehicle (UAV) and a communication, command and control (C3) link between the two systems. UAS are widely used in military …

    vt Repository record for Implementation of a Trusted I/O Processor on a Nascent SoC-FPGA Based Flight Controller for Unmanned Aerial Systems (opens in a new tab)