Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 8 of 8 for “"Memory consistency model"”.
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Efficient coherence and consistency for specialized memory hierarchies
… of specialization. This thesis redesigns the memory hierarchy of heterogeneous systems to make heterogeneous systems more efficient and easier to use. In particular, we focus on three key sources of inefficiency in the memory hierarchy of modern heterogeneous systems: (1) a unified global …
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Optimizing high locality memory references in cache coherent shared memory multi-core processors
Optimizing memory references has been a primary research area of computer systems ever since the advent of the stored program computers. The objective of this thesis research is to identify and optimize two classes of high locality data memory reference streams in cache coherent shared memory …
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Software lock elision for x86 machine code
… of intense research there is no transactional memory hardware nor any examples of software transactional memory use outside the research community. Using software transactional memory in large pieces of software needs copious source code annotations and often means that standard compilers and …
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Samhita: Virtual Shared Memory for Non-Cache-Coherent Systems
… platforms and application domains. The shared memory programming model effectively addresses the parallelism needs of mainstream computing (e.g., portable devices, laptops, desktop, servers), giving rise to a growing ecosystem of shared memory parallel techniques, tools, and design practices. …
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Scalable and flexible bulk architecture
… to improve the programmability of shared-memory architectures. Specifically, we focus on supporting Sequential Consistency (SC), a strong and intuitive memory consistency model. The first part of the thesis focuses on enforcing SC by chunk-based execution. I propose techniques to remove …
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Formal Specification and Runtime Verification of Parallel Systems using Interval Temporal Logic (ITL)
… multi-core processor architecture. The proposed model can check system behaviour at runtime in order to either guarantee satisfaction or detect violations of correctness properties. My technique is based on Interval Temporal Logic (ITL) and its executable subset Tempura to verify properties at …
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Locality-aware cache hierarchy management for multicore processors
… massive data scales. These two factors impact memory access latency and energy consumption adversely. This thesis proposes scalable efficient mechanisms that improve effective cache capacity (i.e., by improving utilization) and reduce data movement by exploiting locality and controlling …
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Specialization without complexity in heterogeneous memory systems
… loosely coupled and lacked a shared coherent memory interface, so specialization was reserved for highly regular code patterns with coarse-grained synchronization requirements. More recently, the need to accelerate applications with more irregular and fine-grained sharing patterns has led to …