Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 19 of 19 for “"Memory Subsystem"”.
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An FPGA implementation of multicore, multithreaded powerPC processors with memory subsystem using Bluespec
… and integration of a multicore processor and a memory subsystem. The work is part of a joint project with IBM Watson research. The processors have multithreading capacities and implement the PowerPC ISA. The memory system consists of a parameterizable hierarchy of caches and random access memory …
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Enabling Approximate Storage through Lossy Media Data Compression
Memory capacity, bandwidth, and energy all continue to present hurdles in the quest for efficient, high-speed computing. Recognition, mining, and synthesis (RMS) applications in particular are limited by the efficiency of the memory subsystem due to their large datasets and need to frequently …
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Workload-aware Page Management
Reservation of free memory in operating systems presents a trade-off between prevention of memory shortage and providing applications a larger cache. Current operating systems use static memory thresholds to control memory subsystem behavior. For example, the free page wake up threshold determines …
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Machine learning feature selection for tuning memory page swapping
This thesis is an exploration of the virtual memory subsystem in the modern Linux kernel. It applies machine learning to find areas where better page-out decisions can be made. Two areas of possible improvement are identified and analyzed. The first area explored arises because pages in a …
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High Performance Architecture using Speculative Threads and Dynamic Memory Management Hardware
… central processing unit (CPU) performance and memory subsystem performance. More specifically I will describe my research related to the design of an innovative decoupled multithreaded architecture that can be used in multi-core processor implementations. I also address how memory management …
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Analysis of CRAY-1S Using Dataflow Graphs.
… approach is demonstrated by modeling the CPU-memory subsystem of the CRAY-1S computer. The resulting model is simulated to obtain timing ang resource usage statistics using as input a control stream that represents the instruction and data stream in the real computer system. The results …
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NON-VOLATILE IN-MEMORY COMPUTING WITH SKYRMIONS AND PHASE CHANGE MEMORIES
The non-volatile in-memory compute engine (NVIMCE), which saves on the latency and energy associated with data movement between memory and processing elements in the conventional von Neumann architectures, is a crucial design technique for enabling ultra-low power intelligent edge devices. Due to …
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GSI: a GPU stall inspector to characterize the sources of memory stalls for tightly coupled GPUs
… to improve the efficiency of heterogeneous memory systems, but current methods for evaluating the performance effects of these innovations are limited in their ability to attribute differences in execution time to sources of latency in the memory system. Performance characterization of …
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Reverse Engineering the Intel Cascade Lake Mesh Interconnect
… for efficient communication between the cores, memory subsystem, and other processor peripherals. Intel’s latest line of Scalable processors introduced the mesh interconnect in the form of a two-dimensional network of rings that reduces the bandwidth and latency bottlenecks of prior ring …
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Next-generation safety-critical systems using COTS based homogeneous multi-core processors and heterogeneous MPSoCS
… processors and MPSoCs is having a shared memory subsystem. Having shared memory for multicore processors suits well for systems where the average-case performance of the system is the performance metric. However, this is not suitable for safety-critical systems where the developer is …
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Prefetching Vs The Memory System : Optimizations for Multi-core Server Platforms
… scheme for servers with respect to realistic memory systems. A large body of research work has been done in prefetching, even for server workloads that have sparse locality. Real systems disable prefetching in server settings, suggesting that there is a fundamental disconnect between research …
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Memory hierarchy and data communication in heterogeneous reconfigurable SoCs
… in contemporary technology development. Memory organization in such heterogeneous reconfigurable architectures becomes very critical. Two primary aspects introduce a sophisticated trade-off. On the one hand, a memory subsystem should provide well organized distributed data structure and …
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A characteristic study of memory over the compute eXpress link
Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01
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Efficient Computation of Map-scale Continuous Mutual Information on Chip in Real Time
… high-efficiency MI compute core and an optimized memory subsystem that provides sufficient bandwidth to keep the cores fully utilized. The core employs interleaving to counter the recursive algorithm, and workload balancing and numerical approximations to reduce latency and energy consumption. We …
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Characterization of FPGA-based High Performance Computers
… of CPU cores per processor exacerbate the memory wall, hybrid core computing, utilizing CPUs augmented with FPGAs and/or GPUs holds the promise of addressing high-performance computing demands, particularly with respect to performance, power and productivity. While traditional approaches to …
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Exploring Dynamic Compilation and Cross-Layer Object Management Policies for Managed Language Applications
… additional safety guarantees, automatic memory and thread management, and dynamic program composition, which have largely driven their success. To support and facilitate the use of these features, virtual machines implement a number of services that adaptively manage and optimize …
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EMACS: efficient CXL-based memory access counters
Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01
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Efficient design and optimized crash-consistency support for hybrid memory systems
Hybrid memory systems (HMSs) pair different memory technologies within a uni ed main memory to combine the best features of those technologies, such as performance with capacity and durability. However, HMSs do not provide a cost-effective solution as a memory subsystem that can accommodate an …
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Systems and applications for persistent memory
… their storage in addition to larger capacity memory at lower cost. While the existing storage technologies (e.g., HDD and flash-based SSD) are limited in their performance, the most prevalent memory technology (DRAM) is unable to address the capacity and cost requirements of these …