Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 23 for “"Memory Controller"”.
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Mitigating Memory Controller Side Channels
Memory timing side channels, where attackers utilize contention within DRAM controllers to infer a victim’s secrets, pose an important challenge to secure computation in shared memory environments. Attacks utilizing these side channels are broad and highly effective, as memory controllers offer a …
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Design of an addressable memory controller.
The main memory is an essential subsystem in a Von Neumann type of stored program machine. Because of the speed gap existence between the processor and the main memor>% there has been a constant need to improve the main memor\' to achieve a better throughput. One method is to use a CAM(Content …
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Optimizing throughput architectures for speculative parallelism
… most likely to help, the core pipeline and the memory controller. First, this thesis presents speculation-aware multithreading (SAM), a simple policy that modifies a multithreaded processor pipeline to prioritize instructions from less speculative tasks. Second, we modify the on-chip memory …
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Characterizing Retention behavior of DDR4 SoDIMM
… factor of our progress is the size and speed of memory we possess. Modern computer architectures use DDR4-based DRAM (Dynamic Random Access Memory) to hold all the immediate information for processing needs. Each bit in a DRAM memory module is implemented with a tiny capacitor and a transistor. …
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Built-in controller for self-test and repair of 3D integrated Nand flash memory chip, used in radiation intense space environment
The perennial need for memory storage is further increasing with the advancements in technology. Both terrestrial and space related applications thrive on efficient ways and new technology for storing data that is incorruptible and dependable. Research is continuously carried out on making storage …
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Optically-Connected Memory: Architectures and Experimental Characterizations
… systems are driving the development of processor-memory interconnects with greater performance and flexibility than can be provided by existing electronic interconnects. A redesign of the systems' memory devices and architectures will be essential to enabling high-bandwidth, low-latency, …
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DESIGN OF A MULTI DSP SYSTEM FOR IMAGE PROCESSING
… specially designed shared dual port dual access memory unit that sits in between two digital signal processors. The dual access memory unit consists of a few sub-modules being integrated together and is programmed by both digital signal processors to operate in one of its several operating modes. …
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Framework for Automatic Translation of Hardware Specifications Written in English to a Formal Language
… specifications taken from the documents of AMBA, memory controller, and UART architectures. The results showed that highly expressive specifications could be handled in our BINGO model. It also demonstrated the ease of creating rules to generate the same semantic frame for specifications with the …
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Utilization-adaptive Memory Architectures
… this dissertation proposes Utilization-adaptive Memory Architectures that enhance the memory controller with the ability to adapt to current memory utilization and implement techniques to boost system performance. These techniques fall under two categories: (i) The techniques under …
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CPU Transparent Protection of OS Kernel and Hypervisor Integrity with Programmable DRAM
… guard that is integrated with the advanced memory buffer of FB-DIMM to continuously monitor all the memory traffic and detect the system integrity violations. Unlike the existing approaches that are either snapshot-based or lack compatibility and flexibility, MGuard continuously monitors the …
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Hardware Memory Compression for Large-scale Systems
Memory has become an increasingly costly resource for both users and service providers, while also contributing significantly to global energy consumption and environmental impact. Memory compression offers a promising solution to mitigate these costs, as memory values exhibit an average …
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Integration and Evaluation of Cache Coherence Protocols for Multiprocessor SoCs
… coherence in a new cache coherence-enforced memory controller. The simulations based on micro-benchmark and RTOS kernel showed the benefits of my methodologies over a generic software solution. This thesis also evaluated and quantified the efficiency of coherence traffic based on a novel …
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Formal Specification and Runtime Verification of Parallel Systems using Interval Temporal Logic (ITL)
… the case study of private L2 cache memory of multi-core processor architecture. My objectives are to i) design MSI protocol compliant with cache memory coherence and ii) fulfil main memory consistency model at runtime. I achieve this via a formal Tempura specification of the cache …
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Toward time-predictable execution of multi-task real-time systems
… also other supportive components such as cache memory, network on chip (NoC), memory controllers. These three components are designed to improve the system computational throughput through either bringing data closer to the processors (e.g cache memory) or maximizing concurrency in moving data …
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Near-Memory Processing for Low-precision Deep Neural Networks
… them good candidates to be considered for near-memory processing due to these criteria. On the other hand, when it comes to designing a hardware module (either for near-memory processing or not), the more specialised the hardware the better the performance. The downside with over-specialised …
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Oblivious RAM : from theory to practice
… We have deployed the design as the on-chip memory controller for a 25 core processor. This proves the viability of a single-chip secure processor that can prevent software IP or data theft through a program's access pattern to main memory (having applications to computation outsourcing and …
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Design and prototyping of Hardware-Accelerated Locality-aware Memory Compression
… for one of such functions namely "Locality-Aware memory compression" which is part of the "OS-controlled memory compression" scheme that has been actively deployed in today's OSes. In brief, OS-controlled memory compression is a new memory management feature that transparently, dramatically, and …
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Prototyping Hardware-compressed Memory for Multi-tenant Systems
Software memory compression has been a common practice among operating systems. Since then, prior works have explored hardware memory compression to reduce the load on the CPU by offloading memory compression to hardware. However, prior works on hardware memory compression cannot provide critical …
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Energy-aware Thread and Data Management in Heterogeneous Multi-Core, Multi-Memory Systems
… multicore processors typically equip multiple memory subsystems to improve data throughput. In addition, these systems employ heterogeneous processors such as GPUs and heterogeneous memories like non-volatile memory to improve performance, capacity, and energy efficiency. With the increasing …
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Next-generation safety-critical systems using COTS based homogeneous multi-core processors and heterogeneous MPSoCS
… processors and MPSoCs is having a shared memory subsystem. Having shared memory for multicore processors suits well for systems where the average-case performance of the system is the performance metric. However, this is not suitable for safety-critical systems where the developer is …
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