Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 22 for “"Memory Access Patterns"”.
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Prefetching for complex memory access patterns
… particularly those in big data, are heavily memory-latency bound. This is because of both irregular memory accesses, which have no discernable pattern in their memory addresses, and large data sets that cannot fit in any cache. However, this need not be a barrier to high performance. With …
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Memory access patterns and page promotion in hybrid memory systems
Hybrid heterogeneous memory systems are becoming increasingly popular as traditional memory systems are hitting performance and energy walls in processing data-intensive applications, which are becoming the norm with the resurgence of machine learning, big data, graph analytics, and database …
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Analysis of Memory Access Patterns for Large Language Model Inference
The use of tiered heterogeneous memory systems in HPC workloads is growing in popularity as the increasing memory requirements for these workloads outpace the decline in the cost- per-gigabyte of fast DRAM; however, the Linux kernel has no intelligent strategy to manage these tiered memory systems. …
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Oblivious RAM in Scalable SGX
… the encrypted ciphertext as well as a program's memory access patterns. As the attacks grow in complexity and accuracy, innovative protection methods must be de- signed to secure data. This thesis proposes and implements an ORAM controller primitive in TEE and protects it from all potential …
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Efficient Support for Speculative Tasking
… called for signatures in hardware to accelerate memory disambiguation. To take full advantage of signatures, this thesis presents SoftBulk, a novel architecture that exposes signatures to software directly through the instruction set. Using SoftBulk, programs can collect information about their …
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DSM64: A Distributed Shared Memory System in User-Space
… release consistent software distributed shared memory (SDSM) system built entirely in user-space. The DSM64 system is capable of executing threaded applications implemented with pthreads on a cluster of networked machines without any modifications to the target application. The DSM64 system …
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Validating performance and simplicity of highly concurrent data structures utilitizing the ATAC broadcast mechanism
… scalable concurrent data structures. Shared memory communication is replaced, alleviating the contention that prevents data structures from achieving high performance on the next generation of manycore computers. The alternative model utilizes thread local memory and relies on the ATAC …
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Dynamic loop vectorization for executing OpenCL kernels on CPUs
… opportunities can be extracted when possible and memory access patterns can be improved. The transformations presented show promising speedups for kernels that follow GPU programming best practices, and slowdowns for kernels that do not.
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Interprocedural Parallelization Using Memory Classification Analysis
… on a combination of techniques: for representing memory accesses within interprocedural. sections of code, for summarizing dependence information in program contexts, and for testing that dependence. The thesis presents a new technique for summarizing the memory access activity in an arbitrary …
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Preliminary Investigation of Productivity Tools for Memory Profiling in Parallel Programs
… depends on whether a program is compute-bound or memory-bound. Memory-bound computations especially benefit from program transformations that improve their data locality, to better exploit modern memory hierarchies. Reuse distance is a useful measure for analyzing data locality in an …
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Characterization of Sparsity-aware Optimization Paths for Graph Traversal on FPGA
… gate array (FPGA) due to its irregular memory-access patterns. Prior work, based on hardware description languages (HDLs) and high-level synthesis (HLS), address the memory-access bottleneck of BFS by using techniques such as data alignment and compute-unit replication on FPGAs. The …
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STATIC ENFORCEMENT OF TERMINATION-SENSITIVE NONINTERFERENCE USING THE C++ TEMPLATE TYPE SYSTEM
… e.g., power usage, execution time, or page fault patterns. A side-channel attack occurs when a malicious adversary observes program secrets through a side channel. This dissertation introduces Covert C++, a library which uses template metaprogramming to superimpose a security-type system on top of …
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Unified RAW Path Oblivious RAM
… is a cryptographic primitive that conceals memory access patterns to untrusted storage. Its applications include oblivious cloud storage, trusted processors, software protection, secure multi-party computation, and so on. This thesis improves the state-of-the-art Path ORAM in several …
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Reducing Global Memory Accesses in DNN Training using Structured Weight Masking
… neural networks (DNNs) is often constrained by memory bandwidth, with frequent global memory accesses representing a significant performance bottleneck. This thesis investigates the potential of dynamic structured weight masking to alleviate this bottleneck during training, focusing on the …
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Sanctum : minimal architectural extensions for isolated execution
… that infer private information from a program's memory access patterns. Sanctum shuns unnecessary complexity, leading to a simpler security analysis. We follow a principled approach to eliminating entire attack surfaces through isolation, rather than plugging attack-specific privacy leaks. Most …
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Mitigating Memory Controller Side Channels
Memory timing side channels, where attackers utilize contention within DRAM controllers to infer a victim’s secrets, pose an important challenge to secure computation in shared memory environments. Attacks utilizing these side channels are broad and highly effective, as memory controllers offer a …
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Ascend : an architecture for performing secure computation on encrypted data
… uses Oblivious RAM (ORAM) techniques to hide memory access patterns and differential-power analysis (DPA) resistance techniques to hide data-dependent power draw. For each of the input/output and power channels, an Ascend chip exposes a set of public knobs that fully specify the observable …
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High Performance Large Graph Analytics by Enhancing Locality
… reference refers to the phenomenon of frequently accessing the same memory location or adjacent memory locations. Applications with poor data locality reduce the effectiveness of the cache memory. They result in large number of cache misses, requiring access to high latency main memory. Therefore, …
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Reducing Cache Contention On GPUs
… of the GPU execution model and the resulting memory accesses cause the GPU memory hierarchy to suffer from significant memory resource contention among threads. One cause of cache contention arises from column-strided memory access patterns that GPU applications commonly generate in many …
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A mesh architecture for data management of matrix computations.
… design. The MDML integrates off-the- shelf memory and processing cores into a scalable on-chip mesh array. The MDML uses a flexible sequencing regime capable of autonomously generating memory access patterns for a variety of complex data structures. This sequencer has been tested by …
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