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Showing 1 to 7 of 7 for “"Manycore Architectures"”.

  1. On-chip wireless manycore architectures

    Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2023-12-01

    uiuc Repository record for On-chip wireless manycore architectures (opens in a new tab)

  2. Exploiting on-chip memory concurrency in 3d manycore architectures

    … thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases in memory-level concurrency. This in turn affects the design of the multi-core interconnect and organization of the memory hierarchy. The work addresses the …

    gatech Repository record for Exploiting on-chip memory concurrency in 3d manycore architectures (opens in a new tab)

  3. Methodologies, Architectures, and Prototypes for Scaling On- and Off-Chip Interconnects

    … first part of this thesis focuses on OCNs for manycore architectures. I first present PyOCN, a unified Python-based framework for modeling, testing, and evaluating on-chip networks, which vertically integrates multiple research methodologies and enables productive design space exploration of …

    cornell Repository record for Methodologies, Architectures, and Prototypes for Scaling On- and Off-Chip Interconnects (opens in a new tab)

  4. Towards low-power yet high-performance networks-on-chip

    … (NoC), the de-facto communication backbone in manycore processors, consumes a significant portion of total chip power, competing against the computation cores for the limited power and thermal budget. On the other hand, overall system performance of manycore chips increasingly relies on on-chip …

    mit Repository record for Towards low-power yet high-performance networks-on-chip (opens in a new tab)

  5. Adaptation of the MapReduce programming framework to compute-intensive data-analytics kernels

    … accelerator, whether GPUs (NVIDIA or AMD), other manycore architectures (like Intel Larrabee or MIC) or even heterogeneous chips (AMD Fusion or IBM Cell processor), there is a fundamental condition imposed on the software, namely the increased sensitivity to locality. As a result, the common theme …

    uiuc Repository record for Adaptation of the MapReduce programming framework to compute-intensive data-analytics kernels (opens in a new tab)

  6. Power and energy management of modern architectures in adaptive HPC runtime systems

    … innovations such as the proposed Exascale architectures and Near Threshold Computing are expected to improve power efficiency significantly, but more innovations are required in this domain to make Exascale possible. To help shrink the power efficiency gap, we argue that adaptive runtime …

    uiuc Repository record for Power and energy management of modern architectures in adaptive HPC runtime systems (opens in a new tab)

  7. Παράλληλοι αλγόριθμοι και εφαρμογές σε πολυπύρηνες μονάδες επεξεργασίας γραφικών

    Στην παρούσα διατριβή παρουσιάζονται παράλληλοι αλγόριθμοι και εφαρμογές σε πολυπύρηνες μονάδες επεξεργασίας γραφικών. Πιο συγκεκριμένα, εξετάζονται οι μέθοδοι σχεδίασης ενός παράλληλου αλγορίθμου για την επίλυση τόσο απλών και κοινών προβλημάτων, όπως η ταξινόμηση, όσο και υπολογιστικά απαιτητικών …

    patras-thes Repository record for Παράλληλοι αλγόριθμοι και εφαρμογές σε πολυπύρηνες μονάδες επεξεργασίας γραφικών (opens in a new tab)