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Showing 1 to 19 of 19 for “"Many-core architectures"”.

  1. Parallel merge for many-core architectures

    This thesis proposes a novel GPU implementation for merging two sorted arrays. We consider the problem of merging two arrays A and B into a single array C. Each element in the arrays has a key. An ordering relation denoted by is defined on the keys. Array A and array B have m and n elements, …

    uiuc Repository record for Parallel merge for many-core architectures (opens in a new tab)

  2. Novel many-core architectures for energy-efficiency

    … the power wall: Processor chips can include more cores and accelerators than can be active at any given time - and the situation is getting worse. This effect, utilization wall or dark silicon, as induced by the power wall, presents a fundamental challenge that is transforming the many-core

    uiuc Repository record for Novel many-core architectures for energy-efficiency (opens in a new tab)

  3. Simulating Nonlinear Neutrino Oscillations on Next-Generation Many-Core Architectures

    … the latter of which is based on the Intel Many Integrated Core Architecture (MIC). The performance of XFLAT on various system configurations and physics scenarios has been analyzed. In addition, the impact of I/O and the multi-node configuration on the Xeon Phi-equipped heterogeneous …

    unm Repository record for Simulating Nonlinear Neutrino Oscillations on Next-Generation Many-Core Architectures (opens in a new tab)

  4. Cu2cl: a Cuda-To-Opencl Translator for Multi- and Many-Core Architectures

    … in order to utilize additional multi- or many-core devices. On the other hand, OpenCL provides an open and vendor-neutral programming environment and run-time system. With implementations available for CPUs, GPUs, and other types of accelerators, OpenCL therefore holds the promise of a …

    vt Repository record for Cu2cl: a Cuda-To-Opencl Translator for Multi- and Many-Core Architectures (opens in a new tab)

  5. Many-core architectures with time predictable execution Support for hard real-time applications

    … by these systems. Generic general-purpose architectures even with the use of real-time operating systems fail to meet the hard realtime constraints of hybrid system dynamics. ASIC, FPGA, or traditional embedded design approaches to these systems often result in expensive, complicated …

    mit Repository record for Many-core architectures with time predictable execution Support for hard real-time applications (opens in a new tab)

  6. Scalable parallel tridiagonal algorithms with diagonal pivoting and their optimization for many-core architectures

    … are commonly performance-sensitive. Recently, many-core architectures, such as GPUs, have become ubiquitous targets for these applications. Therefore, a high-performance general-purpose GPU tridiagonal solver becomes critical. However, no existing GPU tridiagonal solver provides comparable …

    uiuc Repository record for Scalable parallel tridiagonal algorithms with diagonal pivoting and their optimization for many-core architectures (opens in a new tab)

  7. Program Optimization Strategies for Data-Parallel Many-Core Processors

    … application configurations for data-parallel, many-core architectures. Instead of applying a particular phase ordering of optimizations, it starts with an optimization space of major transformations and then reduces the space by examining the static code and pruning configurations that do not …

    uiuc Repository record for Program Optimization Strategies for Data-Parallel Many-Core Processors (opens in a new tab)

  8. On The Parallelization Of Integer Polynomial Multiplication

    … of hardware accelerator technologies, multi-core processors and GPUs, much effort for taking advantage of those architectures by designing parallel algorithms has been made. To achieve this goal, one needs to consider both algebraic complexity and parallelism, plus making efficient use of …

    uwo Repository record for On The Parallelization Of Integer Polynomial Multiplication (opens in a new tab)

  9. Exploiting on-chip memory concurrency in 3d manycore architectures

    The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases in memory-level concurrency. This in turn affects the design of the multi-core interconnect and organization of the memory hierarchy. The …

    gatech Repository record for Exploiting on-chip memory concurrency in 3d manycore architectures (opens in a new tab)

  10. HARP: A MACHINE LEARNING FRAMEWORK ON TOP OF THE COLLECTIVE COMMUNICATION LAYER FOR THE BIG DATA SOFTWARE STACK

    … has evolved towards computers exhibiting many-core architectures of increasing complexity. However, there is no simple and unified programming framework allowing for these machine learning applications to exploit these new machines’ parallel computing capability. Instead, many efforts …

    iu Repository record for HARP: A MACHINE LEARNING FRAMEWORK ON TOP OF THE COLLECTIVE COMMUNICATION LAYER FOR THE BIG DATA SOFTWARE STACK (opens in a new tab)

  11. Safe Concurrent Programming and Execution

    The increasing prevalence of multi and many core processors has brought the issues of concurrency and parallelism to the forefront of everyday computing. Even for applications amenable to traditional parallelization techniques, the subtleties of concurrent programming are known to introduce …

    vt Repository record for Safe Concurrent Programming and Execution (opens in a new tab)

  12. Improving the performance of parallel scientific applications using cache injection

    … injection policy. This result implies that multi-core and many-core architectures would benefit from this technique. Finally, my results show that the application's communication characteristics are key to cache injection performance. For example, cache injection can improve the performance of …

    unm Repository record for Improving the performance of parallel scientific applications using cache injection (opens in a new tab)

  13. Proximity coherence for chip-multiprocessors

    Many-core architectures provide an efficient way of harnessing the growing numbers of transistors available in modern fabrication processes; however, the parallel programs run on these platforms are increasingly limited by the energy and latency costs of communication. Existing designs provide a …

    cambridge Repository record for Proximity coherence for chip-multiprocessors (opens in a new tab)

  14. Compilation techniques and language support to facilitate dependence-driven computation

    … in modern computer runtime systems and architectures, programmers are left with the daunting challenge of fully exploiting these systems for efficiency, high-level expressibility, and portability across different computing architectures. Emerging programming models such as the task-based …

    uiuc Repository record for Compilation techniques and language support to facilitate dependence-driven computation (opens in a new tab)

  15. A distributed multi-threaded data partitioner with space-filling curve orders

    … data partitioning and data re-ordering on many-core architectures. We present extensive literature survey, with examples from various application domains - scientific computing, databases and large-scale graph processing. We propose a low-overhead partitioning framework based on geometry, …

    uiuc Repository record for A distributed multi-threaded data partitioner with space-filling curve orders (opens in a new tab)

  16. Samhita: Virtual Shared Memory for Non-Cache-Coherent Systems

    … of computing today are the emergence of many-core architectures and the resulting need to effectively exploit explicit parallelism. Indeed, programmers are striving to exploit parallelism across virtually all platforms and application domains. The shared memory programming model …

    vt Repository record for Samhita: Virtual Shared Memory for Non-Cache-Coherent Systems (opens in a new tab)

  17. Autonomic behavioural framework for structural parallelism over heterogeneous multi-core systems.

    … the latest developments in heterogeneous multi-core/many-core architectures. Structural programming paradigms propose a viable solution for e ciently programming modern heterogeneous multi-core architectures equipped with one or more programmable Graphics Processing Units (GPUs). Applying …

    rgu Repository record for Autonomic behavioural framework for structural parallelism over heterogeneous multi-core systems. (opens in a new tab)

  18. Optimizing for a Many-Core Architecture without Compromising Ease-of-Programming

    … improvements. But even though numerous parallel architectures have already been brought to market, a universally accepted methodology for programming them for general purpose applications has yet to emerge. Existing solutions tend to be hardware-specific, rendering them difficult to use for the …

    maryland Repository record for Optimizing for a Many-Core Architecture without Compromising Ease-of-Programming (opens in a new tab)

  19. Data layout transformation through in-place transposition

    … is an important algorithmic building block for many numeric algorithms like multidimensional FFT. It has also been used to convert the storage layout of arrays. Intuitively, in-place transposition should be a good fit for GPU architectures due to limited available on-board memory capacity and …

    uiuc Repository record for Data layout transformation through in-place transposition (opens in a new tab)