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Showing 1 to 14 of 14 for “"MOS transistor"”.

  1. Measurement and modeling of small-geometry MOS transistor capacitances

    Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1984.

    mit Repository record for Measurement and modeling of small-geometry MOS transistor capacitances (opens in a new tab)

  2. Effective mobility in silicon surface channels as measured with the MOS transistor

    … effective mobility theory to silicon and to the MOS transistor, and b) extension of the existing effective mobility theory by the removal of various simplifying assumptions. Mobility measurements were confined primarily to inversion p-channel MOS transistors, although some built-in-channel and …

    uiuc Repository record for Effective mobility in silicon surface channels as measured with the MOS transistor (opens in a new tab)

  3. Investigations of the Electric Field Dependencies of the Generation Rates of Oxide and Interface Traps on Silicon

    A bipolar-MOS transistor (BIMOS) is employed to investigate the electric field dependencies of the oxide and interface trap generation and charging on oxidized silicon film on silicon. The substrate emitter/base junction is forward-biased to independently control the current injected into the gate …

    uiuc Repository record for Investigations of the Electric Field Dependencies of the Generation Rates of Oxide and Interface Traps on Silicon (opens in a new tab)

  4. Broadband mm-wave signal generation and amplification in CMOS using synthetic impedance

    … between the drain voltage and drain current of a MOS transistor. A high frequency, wide tuning range 105-121GHz oscillator and a small-footprint 20-40GHz oscillator using synthetic resonance are presented. The concept of impedance synthesis is also used to generate a novel frequency-adaptive loss …

    mit Repository record for Broadband mm-wave signal generation and amplification in CMOS using synthetic impedance (opens in a new tab)

  5. Design methodology for electron-trap memory cells

    … improvement will eventually come to an end. The MOS transistor itself cannot overcome its limits dictated by its operating principle. In order to ensure further feature size reduction, the field of single-electronics has been developed. Single Electron Tunneling (SET) technology offers the …

    windsor Repository record for Design methodology for electron-trap memory cells (opens in a new tab)

  6. Analog circuit optimization using evolutionary algorithms and convex optimization

    … for producing accurate posynomial models for MOS transistor parameters, which is the first step of the decomposition. The new algorithm can generate posynomial models with variable number of terms and real-valued exponents. The algorithm is a hybrid of a genetic algorithm and a convex …

    mit Repository record for Analog circuit optimization using evolutionary algorithms and convex optimization (opens in a new tab)

  7. Fully integrated ultra low voltage cold start system for thermal energy harvesting . . .

    … components. An optimized depletion mode MOS transistor was fabricated and tested with an off-chip transformer, to exhibit oscillations from <3 mV DC input voltage. An optimized on-chip transformer, 36x smaller in area than the off-chip transformers, is currently awaiting layout and …

    mit Repository record for Fully integrated ultra low voltage cold start system for thermal energy harvesting . . . (opens in a new tab)

  8. Low-Voltage Analog CMOS Architectures and Design Methods

    … at VT + 2Vds,sat, the minimum supply for CMOS circuits with all transistors in the active region where Vds,sat is the drain to source saturation voltage of a MOS transistor. Techniques which meet this criteria for rail-to-rail input stages, gain enhancement stages, and output stages are …

    byu Repository record for Low-Voltage Analog CMOS Architectures and Design Methods (opens in a new tab)

  9. Ultra-low noise and low temperature drift power supply system design for RF applications

    … integrated into cost effective and widely used CMOS process, because they are realized in expensive technologies and they need off-chip components to filter low frequency noise. A novel circuit technique to correct the temperature drift and achieve low noise performance is proposed. The …

    mit Repository record for Ultra-low noise and low temperature drift power supply system design for RF applications (opens in a new tab)

  10. An Exploration of Entropy Sources in Standard CMOS for Cryptographic Applications

    … by utilising a metal oxide semiconductor (MOS) capacitor structure, realised by grounding the drain and source of a MOS transistor. The thin oxide layer between the gate-bulk and the gate-drain, and gate-source presents a potential barrier that provides ideal tunnelling conditions. Devices …

    unsw Repository record for An Exploration of Entropy Sources in Standard CMOS for Cryptographic Applications (opens in a new tab)

  11. Visible and Infrared Light Detection Using 2D Materials

    … potential for pushing electronic devices, from transistors to photovoltaics, to the atomic limit. In particular, many transition metal dichalcogenides such as tungsten diselenide (WSe₂) have properties such as a large absorption coefficient, ambipolar nature, and a bandgap near ~1.34 eV that …

    mit Repository record for Visible and Infrared Light Detection Using 2D Materials (opens in a new tab)

  12. Efficient IC statistical modeling and extraction using a Bayesian inference framework

    … and extraction by combining an ultra-compact transistor model, called the MIT virtual source (MVS) model, and a Bayesian extraction method. Based on statistical formulations extended from the MVS model, we propose algorithms for three applications that greatly reduce time and cost required for …

    mit Repository record for Efficient IC statistical modeling and extraction using a Bayesian inference framework (opens in a new tab)

  13. Analysis and Design of Wide Tuning Range Low Phase Noise mm-wave LC-VCOs

    … bottom-biased and top-biased cross-coupled pair CMOS LC-VCOs in order to cancel the fixed parasitic capacitance in the LC-tank. Various NC circuits with low power consumption are designed and analyzed. A figure of merit (FOM) is proposed to compare the performance of different NC circuits. A power …

    ohiolink Repository record for Analysis and Design of Wide Tuning Range Low Phase Noise mm-wave LC-VCOs (opens in a new tab)