Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 4 of 4 for “"Low power architecture"”.
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An asynchronous,low-power architecture for interleaved neural stimulation, using envelope and phase information
This thesis describes a low-power cochlear-implant processor chip and a charge-balanced stimulation chip that together form a complete processing-and-stimulation cochlear-implant system. The processor chip uses a novel Asynchronous Interleaved Stimulation (AIS) algorithm that preserves phase and …
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Ultra-dynamic voltage scalable (U-DVS) SRAM design considerations
… of these challenges is the incessant increase of power consumption in integrated circuits. This problem has motivated the industry and academia to pay significant attention to low-power circuit design for the past two decades. Operating digital circuits at lower voltage levels was shown to …
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Ultra low power, high sensitivity secure wake-up receiver for the Internet of Things
… the sensors and nodes have a highly constrained power budget or even operate using a batteryless energy-harvesting scheme. With tons of data being transmitted through the IoT nodes, the specifications dictate an ultra low power design with secure communication. An ultra low power wake-up receiver …
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Αρχιτεκτονικές επεξεργαστών και μνημών ειδικού σκοπού για την υποστήριξη φερέγγυων (ασφαλών) δικτυακών υπηρεσιών
Η ασφάλεια των υπολογιστικών συστημάτων αποτελεί πλέον μια πολύ ενεργή περιοχή και αναμένεται να γίνει μια νέα παράμετρος σχεδίασης ισάξια μάλιστα με τις κλασσικές παραμέτρους σχεδίασης των συστημάτων, όπως είναι η απόδοση, η κατανάλωση ισχύος και το κόστος. Οι φερέγγυες υπολογιστικές πλατφόρμες …