Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 8 of 8 for “"Low Power VLSI"”.
-
Asynchrobatic logic for low-power VLSI design
… Asynchrobatic Logic is presented. It is a novel low-power design style that combines the energy saving benefits of asynchronous logic and adiabatic logic to produce systems whose power dissipation is reduced in several different ways. The term “Asynchrobatic” is a new word that can be used to …
-
Circuits for high-performance low-power VLSI logic
… as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and variation. We propose a new family of logic styles called Preset Skewed Static Logic (PSSL). PSSL …
-
Algorithmic Techniques for Logic Synthesis of Low Power VLSI Circuits
… be used during the logic synthesis phase of the VLSI design flow to reduce the total power consumption in VLSI circuits. These techniques are applicable to circuit implementations based upon static CMOS technology, but are independent of factors such as the specific fabrication process employed …
-
Design of a low power VLSI systems powered by ambient mechanical vibration
Low power design trends raise the possibility of using ambient energy to power future digital systems. This thesis explores the design of such systems for collecting and processing data from sensors. The low throughput requirements of this type of computation allows aggressive scaling of supply …
-
Reliable and Low -Power Signal Processing via Algorithmic Noise -Tolerance
… we address the problem of designing reliable and low-power VLSI systems for communications and DSP applications. An information theoretic framework to derive the lower bound on energy dissipation of VLSI circuits in presence of deep submicron noise is presented. It is shown that error-control …
-
Wireless Neural Recording and Stimulation SoCs for Monitoring and Treatment of Intractable Epilepsy
… wireless transmitter. Each channel contains a low-noise amplifier and a modified 8-bit SAR ADC that and can provide analog-digital multiplication by modifying the ADC sampling phase. It is used in conjunction with 12-bit digital adders and registers to implement 64 16-tap FIR filters with a …
-
Efficient VLSI Implementation of Arithmetic Units and Logic Circuits
… logic circuits are critical components of any VLSI system. Thus realizing efficient arithmetic units and logic circuits is required for better performance of a data path unit and therefore microprocessor or digital signal processor (DSP). Adders are basic building blocks of any processor or …
-
Energy-Efficient On-Chip Cache Architectures and Deep Neural Network Accelerators Considering the Cost of Data Movement
付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」