Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 24 for “"Local memory"”.
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Mapping unstructured mesh codes onto local memory parallel architectures
… scale unstructured problems on a distributed memory machine is the question of how to partition the underlying computational domain efficiently. It is important that all processors are kept busy for as large a proportion of the time as possible and that the amount, level and frequency of …
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Reduction in Main Memory Traffic Through the Efficient Use of Local Memory
Memory referencing behavior is analyzed by studying traces for the purpose of developing new local memory structures and management techniques that reduce the traffic to main memory. A novel trace processing technique called flattening reduces the dependence of the results on the underlying …
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Design of optoelectronic activation, local memory and weighting circuits for Compact Integrated Optoelectronic Neural (COIN) Co-processor
… thresholding (activation), weighting and memory circuits for the COIN processor. The first version involved the design of fixed thresholding and weighting functions. The second version incorporated a local capacitive memory element as well as variable weighting schemes. The third version …
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Tunable shared-memory abstractions for distributed-memory systems
Distributed memory multiprocessor architectures offer enormous computational power, by exploiting the concurrent execution of many loosely connected processors. Yet, such scalability is not without price. Interface delays and low interconnection bandwidth to the distributed memories make internode …
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Programming Abstractions for Scalable and High-Performance Memory Disaggregation
Memory-intensive applications, such as in-memory analytics, databases, and caching, are driving the memory demand in datacenters. Unfortunately, DRAM scaling is challenging as the technology reaches its physical limit. Although its demand continues to rise, memory is an underutilized resource …
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Validating performance and simplicity of highly concurrent data structures utilitizing the ATAC broadcast mechanism
… scalable concurrent data structures. Shared memory communication is replaced, alleviating the contention that prevents data structures from achieving high performance on the next generation of manycore computers. The alternative model utilizes thread local memory and relies on the ATAC …
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Splash-2 shared-memory architecture for supporting high level language compilers
… Many aspects of CCM architectures, such as local memory systems, are not conducive to HLL compiler usage. This thesis proposes and evaluates the use of a shared-memory architecture on a Splash-2 CCM to promote the development and usage of HLL compilers for CCM systems.
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Optimizing directory-based cache coherence on the RAW architecture
Caches help reduce the effect of long-latency memory requests, by providing a high speed data-path to local memory. However, in multi-processor systems utilizing shared memory, cache coherence protocols are necessary to ensure sequential consistency. Of the multiple coherence protocols developed, …
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A hybrid fault injection environment for measuring system dependability
… a physical address, e.g., CPU registers, cache, local memory, mass storage, and network controllers. Faults can also be injected into locations allocated to a single, executing user program or even into the kernel, and propagation can be characterized down to the instruction level. The …
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Delay, stability, and resource tradeoffs in large distributed service systems
… to the dispatcher, and stored in a limited local memory. Our objective is to understand the best possible performance of such systems (in terms of stability region and delay) and to propose optimal policies, with emphasis on the asymptotic regime when both the number of servers and the …
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High Performance Applications for the Single-Chip Message-Passing Parallel Computer
… via a 2-D grid network and each contains a local memory bank. This thesis presents the design and analysis of three high-performance applications for SCMP. The results show that the architecture proves itself as a formidable opponent to several current systems.
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Characterization of Sparsity-aware Optimization Paths for Graph Traversal on FPGA
… gate array (FPGA) due to its irregular memory-access patterns. Prior work, based on hardware description languages (HDLs) and high-level synthesis (HLS), address the memory-access bottleneck of BFS by using techniques such as data alignment and compute-unit replication on FPGAs. The …
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Novel methods for post-manufacturing and in-field testing of VLSI circuits/systems
… cores, the reusability of the tester vector memory (local memory of the test head), the on-chip implementation cost of the decoder and the test power consumption. Moreover, we improve each of the aforementioned parameters without degradation of the compression and test application time …
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Non-Blocking Data Structures Handling Multiple Changes Atomically
… other than updates perform only reads of shared memory. Our doubly-linked list implements a novel specification that is designed to make it easy to use as a black box in a concurrent setting. In our doubly-linked list implementation, each process accesses the list via a cursor, which is an object …
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Distributed policy-based management framework for wireless sensor networks.
… of nodes; and constrained hardware resources. Memory, processing, and battery power are limited, making WSNs capable of handling only applications with limited resource requirements. Consequently, the implementation of policy-based management applications on WSNs has to tackle these …
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Efficient architectures of heterogeneous fpga-gpu for 3-d medical image compression
… Evaluation results are shown for each memory iteration, transfer sizes from GPU to CPU consuming more bandwidth or throughput. For size 786, 486 bytes JPEG format, both directions consumed bandwidth tend to balance. Bandwidth is relative to the transfer size, the larger sizing will take …
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Abstracting the hardware/software boundary through a standard system support layer and architecture
… tasks. This thesis demonstrates that a shared memory multi-threaded programming model with high-level language semantics may be extended to hardware, consequently abstracting the hardware/software boundary. The research for this thesis was conducted in three phases, and used the KU-developed …
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Dynamic weakening and trained memory in avalanche dynamics from high-entropy alloys to neurons and spin systems
… weakening and healing, which temporarily modify local thresholds during and after avalanches. This thesis investigates how weakening and healing govern avalanche dynamics in materials and biological systems, and how avalanche analysis reveals underlying critical points and scaling laws in …
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Memory abstractions for parallel programming
A memory abstraction is an abstraction layer between the program execution and the memory that provides a different "view" of a memory location depending on the execution context in which the memory access is made. Properly designed memory abstractions help ease the task of parallel programming by …
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Memory, Cinema and Deathscapes: Re-membering the Holocaust in Poland
Holocaust memory is at a critical juncture. The intersection of anxieties about survivors and firsthand witnesses growing fewer and frailer, the ever-growing importance and ongoing boom in popular media representations of the Holocaust across the last four decades, and the contemporary threat of …
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