Global ETD Search
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Showing 1 to 9 of 9 for “"Latchup"”.
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Modeling and suppression of latchup
In this dissertation, an experimental study of latchup is conducted. A semi-physical analytical model is proposed that estimates the latchup susceptibility of a design prior to fabrication. The model can easily be implemented in a circuit simulator and be simulated together with the rest of the …
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Comparison of DC latchup characterization techniques for CMOS technology
Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1984.
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A transient analysis and characterization of latchup in bulk CMOS
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1983.
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Investigation of the hazards of substrate current injection: transient external latchup and substrate noise coupling
… current injection is the origin of external latchup and substrate noise coupling. The trigger current for external latchup depends on the duration of the trigger event. A physics-based model is provided to model the effects of aggressor to victim spacing and orientation on transient …
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A method for characterization of single-event latchup technologies as a function of geometric variation
… between the power supply rails known as the “latchup” state. Latchup is destructive and requires a power cycle to restore operation. Latchup can be stimulated by ionizing radiation such as a high-energy proton or heavy-ions from deep space, resulting in a significant vulnerability in CMOS …
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Radiation Damage in CMOS Image Sensors for Space Applications
… silicon thickness) on the rate of Single Event Latchup (SEL) in CMOS Active Pixel Sensor (APS) devices. SEL is a potentially destructive phenomenon which occurs in CMOS technology but not in CCDs. Test devices were subjected to heavy ion bombardement and SEL rates recorded for a range of heavy …
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Techniques for low power analog, digital and mixed signal CMOS integrated circuit design
… for operation at ± 0.4 V. The issue of CMOS latchup and noise has been investigated in detail because of the forward biasing of the substrates of MOSFETs in CMOS. With increasing forward body-bias, the leakage current increases significantly. Dynamic threshold MOSFET (DTMOS) technique is …
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BiCMOS technology and some applications in high performance arithmetic structures.
… technologies, BiCMOS process tradeoffs, and latchup in BiCMOS. Several high performance arithmetic architectures were implemented in the form of macrocells, and their design is discussed. Toward that end, a survey of hardware multipliers is given, concentrating on the parallel types, and two …
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Trade-offs between performance and reliability of sub 100-nm RF-CMOS technologies
… irradiation tolerance is studied [3], [4]. 6) Latchup phenomenon in CMOS is shown to be possible at cryogenic temperatures (below 50 K), and its consequences are discussed [5]. 7) A time-dependent device degradation model has been developed in technology computer aided design (TCAD) to model …